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anv: Access more colors in fast_clear_memory_range

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Store an array of clear values, one for each view format of the image.
Load the clear value based on the view format.

anv_image_msaa_resolve() may override the source or destination with
ISL_FORMAT_UNSUPPORTED, so make anv_image_get_clear_color_addr() handle
that format.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31743>
This commit is contained in:
Nanley Chery 2024-03-25 16:23:54 -04:00 • committed by Marge Bot
parent 43bc4f4576
commit 0e6b132a75
6 changed files with 149 additions and 107 deletions
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3
src/intel/ci/angle-anv-jsl-fails.txt
View file

@ -3,6 +3,9 @@ dEQP-GLES2.functional.shaders.builtin_variable.fragcoord_xyz,Fail
dEQP-GLES3.functional.shaders.builtin_variable.fragcoord_xyz,Fail
multisample-dEQP-GLES3.functional.shaders.builtin_variable.fragcoord_xyz,Fail
# deqp-gles31: ../src/intel/vulkan/anv_private.h:5588: anv_image_get_clear_color_addr: Assertion `anv_image_view_formats_incomplete(image)' failed.
dEQP-GLES31.functional.image_load_store.2d_array.format_reinterpret.rgba8_rgba8i,Crash
# ANGLE marks non-shadow linear-filtered textures incomplete (see GLES 3.2 spec
# 8.17 Texture Completeness), so you get a fallback texture sample, while Mesa
# incorrectly marks it complete. The CTS incorrectly expects texture

131
src/intel/vulkan/anv_blorp.c
View file

@ -271,6 +271,7 @@ get_blorp_surf_for_anv_image(const struct anv_cmd_buffer *cmd_buffer,
VkImageUsageFlags usage,
VkImageLayout layout,
enum isl_aux_usage aux_usage,
enum isl_format view_fmt,
struct blorp_surf *blorp_surf)
{
const struct anv_device *device = cmd_buffer->device;
@ -316,16 +317,12 @@ get_blorp_surf_for_anv_image(const struct anv_cmd_buffer *cmd_buffer,
};
}
if (aspect & VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV) {
const struct anv_address clear_color_addr =
anv_image_get_clear_color_addr(device, image, aspect);
blorp_surf->clear_color_addr = anv_to_blorp_address(clear_color_addr);
} else if (aspect & VK_IMAGE_ASPECT_DEPTH_BIT) {
const struct anv_address clear_color_addr =
anv_image_get_clear_color_addr(device, image, aspect);
blorp_surf->clear_color_addr = anv_to_blorp_address(clear_color_addr);
const struct anv_address clear_color_addr =
anv_image_get_clear_color_addr(device, image, view_fmt, aspect);
blorp_surf->clear_color_addr = anv_to_blorp_address(clear_color_addr);
if (aspect & VK_IMAGE_ASPECT_DEPTH_BIT)
blorp_surf->clear_color = anv_image_hiz_clear_value(image);
}
}
}
@ -374,17 +371,24 @@ copy_image(struct anv_cmd_buffer *cmd_buffer,
if (util_bitcount(src_mask) > 1) {
anv_foreach_image_aspect_bit(aspect_bit, src_image, src_mask) {
enum isl_format src_format, dst_format;
int plane = anv_image_aspect_to_plane(src_image, 1UL << aspect_bit);
blorp_copy_get_formats(&cmd_buffer->device->isl_dev,
&src_image->planes[plane].primary_surface.isl,
&dst_image->planes[plane].primary_surface.isl,
&src_format, &dst_format);
struct blorp_surf src_surf, dst_surf;
get_blorp_surf_for_anv_image(cmd_buffer,
src_image, 1UL << aspect_bit,
VK_IMAGE_USAGE_TRANSFER_SRC_BIT,
src_image_layout, ISL_AUX_USAGE_NONE,
&src_surf);
src_format, &src_surf);
get_blorp_surf_for_anv_image(cmd_buffer,
dst_image, 1UL << aspect_bit,
VK_IMAGE_USAGE_TRANSFER_DST_BIT,
dst_image_layout, ISL_AUX_USAGE_NONE,
&dst_surf);
dst_format, &dst_surf);
anv_cmd_buffer_mark_image_written(cmd_buffer, dst_image,
1UL << aspect_bit,
dst_surf.aux_usage, dst_level,
@ -402,15 +406,23 @@ copy_image(struct anv_cmd_buffer *cmd_buffer,
/* This case handles the ycbcr images, aspect mask are compatible but
* don't need to be the same.
*/
enum isl_format src_format, dst_format;
int s_plane = anv_image_aspect_to_plane(src_image, src_mask);
int d_plane = anv_image_aspect_to_plane(dst_image, dst_mask);
blorp_copy_get_formats(&cmd_buffer->device->isl_dev,
&src_image->planes[s_plane].primary_surface.isl,
&dst_image->planes[d_plane].primary_surface.isl,
&src_format, &dst_format);
struct blorp_surf src_surf, dst_surf;
get_blorp_surf_for_anv_image(cmd_buffer, src_image, src_mask,
VK_IMAGE_USAGE_TRANSFER_SRC_BIT,
src_image_layout, ISL_AUX_USAGE_NONE,
&src_surf);
src_format, &src_surf);
get_blorp_surf_for_anv_image(cmd_buffer, dst_image, dst_mask,
VK_IMAGE_USAGE_TRANSFER_DST_BIT,
dst_image_layout, ISL_AUX_USAGE_NONE,
&dst_surf);
dst_format, &dst_surf);
anv_cmd_buffer_mark_image_written(cmd_buffer, dst_image, dst_mask,
dst_surf.aux_usage, dst_level,
dst_base_layer, layer_count);
@ -631,10 +643,14 @@ copy_buffer_to_image(struct anv_cmd_buffer *cmd_buffer,
{
struct {
struct blorp_surf surf;
struct isl_surf *isl_surf;
enum isl_format copy_format;
uint32_t level;
VkOffset3D offset;
} image, buffer, *src, *dst;
struct isl_surf buffer_isl_surf;
buffer.isl_surf = &buffer_isl_surf;
buffer.level = 0;
buffer.offset = (VkOffset3D) { 0, 0, 0 };
@ -647,13 +663,8 @@ copy_buffer_to_image(struct anv_cmd_buffer *cmd_buffer,
}
const VkImageAspectFlags aspect = region->imageSubresource.aspectMask;
get_blorp_surf_for_anv_image(cmd_buffer, anv_image, aspect,
buffer_to_image ?
VK_IMAGE_USAGE_TRANSFER_DST_BIT :
VK_IMAGE_USAGE_TRANSFER_SRC_BIT,
image_layout, ISL_AUX_USAGE_NONE,
&image.surf);
const unsigned plane = anv_image_aspect_to_plane(anv_image, aspect);
image.isl_surf = &anv_image->planes[plane].primary_surface.isl;
image.offset =
vk_image_sanitize_offset(&anv_image->vk, region->imageOffset);
image.level = region->imageSubresource.mipLevel;
@ -674,13 +685,23 @@ copy_buffer_to_image(struct anv_cmd_buffer *cmd_buffer,
const struct vk_image_buffer_layout buffer_layout =
vk_image_buffer_copy_layout(&anv_image->vk, region);
struct isl_surf buffer_isl_surf;
get_blorp_surf_for_anv_buffer(cmd_buffer,
anv_buffer, region->bufferOffset,
extent.width, extent.height,
buffer_layout.row_stride_B, linear_format,
false, &buffer.surf, &buffer_isl_surf);
blorp_copy_get_formats(&cmd_buffer->device->isl_dev,
src->isl_surf, dst->isl_surf,
&src->copy_format, &dst->copy_format);
get_blorp_surf_for_anv_image(cmd_buffer, anv_image, aspect,
buffer_to_image ?
VK_IMAGE_USAGE_TRANSFER_DST_BIT :
VK_IMAGE_USAGE_TRANSFER_SRC_BIT,
image_layout, ISL_AUX_USAGE_NONE,
image.copy_format, &image.surf);
if (&image == dst) {
anv_cmd_buffer_mark_image_written(cmd_buffer, anv_image,
aspect, dst->surf.aux_usage,
@ -876,16 +897,27 @@ blit_image(struct anv_cmd_buffer *cmd_buffer,
dst_res->aspectMask));
anv_foreach_image_aspect_bit(aspect_bit, src_image, src_res->aspectMask) {
VkFormat src_vk_format =
src_image->emu_plane_format != VK_FORMAT_UNDEFINED ?
src_image->emu_plane_format : src_image->vk.format;
struct anv_format_plane src_format =
anv_get_format_aspect(cmd_buffer->device->info, src_vk_format,
1U << aspect_bit, src_image->vk.tiling);
struct anv_format_plane dst_format =
anv_get_format_aspect(cmd_buffer->device->info, dst_image->vk.format,
1U << aspect_bit, dst_image->vk.tiling);
get_blorp_surf_for_anv_image(cmd_buffer,
src_image, 1U << aspect_bit,
VK_IMAGE_USAGE_TRANSFER_SRC_BIT,
src_image_layout, ISL_AUX_USAGE_NONE, &src);
src_image_layout, ISL_AUX_USAGE_NONE,
src_format.isl_format, &src);
get_blorp_surf_for_anv_image(cmd_buffer,
dst_image, 1U << aspect_bit,
VK_IMAGE_USAGE_TRANSFER_DST_BIT,
dst_image_layout, ISL_AUX_USAGE_NONE, &dst);
VkFormat src_vk_format = src_image->vk.format;
dst_image_layout, ISL_AUX_USAGE_NONE,
dst_format.isl_format, &dst);
if (src_image->emu_plane_format != VK_FORMAT_UNDEFINED) {
/* redirect src to the hidden plane */
@ -896,17 +928,8 @@ blit_image(struct anv_cmd_buffer *cmd_buffer,
anv_image_address(src_image, &surface->memory_range);
src.surf = &surface->isl,
src.addr.offset = address.offset;
src_vk_format = src_image->emu_plane_format;
}
struct anv_format_plane src_format =
anv_get_format_aspect(cmd_buffer->device->info, src_vk_format,
1U << aspect_bit, src_image->vk.tiling);
struct anv_format_plane dst_format =
anv_get_format_aspect(cmd_buffer->device->info, dst_image->vk.format,
1U << aspect_bit, dst_image->vk.tiling);
unsigned dst_start, dst_end;
if (dst_image->vk.image_type == VK_IMAGE_TYPE_3D) {
assert(dst_res->baseArrayLayer == 0);
@ -1280,7 +1303,7 @@ exec_ccs_op(struct anv_cmd_buffer *cmd_buffer,
get_blorp_surf_for_anv_image(cmd_buffer, image, aspect,
0, ANV_IMAGE_LAYOUT_EXPLICIT_AUX,
image->planes[plane].aux_usage,
&surf);
format, &surf);
uint32_t level_width = u_minify(surf.surf->logical_level0_px.w, level);
uint32_t level_height = u_minify(surf.surf->logical_level0_px.h, level);
@ -1344,7 +1367,7 @@ exec_mcs_op(struct anv_cmd_buffer *cmd_buffer,
struct blorp_surf surf;
get_blorp_surf_for_anv_image(cmd_buffer, image, aspect,
0, ANV_IMAGE_LAYOUT_EXPLICIT_AUX,
ISL_AUX_USAGE_MCS, &surf);
ISL_AUX_USAGE_MCS, format, &surf);
/* Blorp will store the clear color for us if we provide the clear color
* address and we are doing a fast clear. So we save the clear value into
@ -1402,7 +1425,7 @@ void anv_CmdClearColorImage(
VK_IMAGE_ASPECT_COLOR_BIT,
VK_IMAGE_USAGE_TRANSFER_DST_BIT,
imageLayout, ISL_AUX_USAGE_NONE,
&surf);
src_format.isl_format, &surf);
union isl_color_value clear_color = vk_to_isl_color(*pColor);
@ -1500,7 +1523,8 @@ void anv_CmdClearDepthStencilImage(
get_blorp_surf_for_anv_image(cmd_buffer,
image, VK_IMAGE_ASPECT_DEPTH_BIT,
VK_IMAGE_USAGE_TRANSFER_DST_BIT,
imageLayout, ISL_AUX_USAGE_NONE, &depth);
imageLayout, ISL_AUX_USAGE_NONE,
ISL_FORMAT_UNSUPPORTED, &depth);
} else {
memset(&depth, 0, sizeof(depth));
}
@ -1509,7 +1533,8 @@ void anv_CmdClearDepthStencilImage(
get_blorp_surf_for_anv_image(cmd_buffer,
image, VK_IMAGE_ASPECT_STENCIL_BIT,
VK_IMAGE_USAGE_TRANSFER_DST_BIT,
imageLayout, ISL_AUX_USAGE_NONE, &stencil);
imageLayout, ISL_AUX_USAGE_NONE,
ISL_FORMAT_UNSUPPORTED, &stencil);
} else {
memset(&stencil, 0, sizeof(stencil));
}
@ -1747,7 +1772,8 @@ anv_fast_clear_depth_stencil(struct anv_cmd_buffer *cmd_buffer,
get_blorp_surf_for_anv_image(cmd_buffer,
image, VK_IMAGE_ASPECT_DEPTH_BIT,
0, ANV_IMAGE_LAYOUT_EXPLICIT_AUX,
image->planes[plane].aux_usage, &depth);
image->planes[plane].aux_usage,
ISL_FORMAT_UNSUPPORTED, &depth);
}
struct blorp_surf stencil = {};
@ -1757,7 +1783,8 @@ anv_fast_clear_depth_stencil(struct anv_cmd_buffer *cmd_buffer,
get_blorp_surf_for_anv_image(cmd_buffer,
image, VK_IMAGE_ASPECT_STENCIL_BIT,
0, ANV_IMAGE_LAYOUT_EXPLICIT_AUX,
image->planes[plane].aux_usage, &stencil);
image->planes[plane].aux_usage,
ISL_FORMAT_UNSUPPORTED, &stencil);
}
/* From the Sky Lake PRM Volume 7, "Depth Buffer Clear":
@ -2052,16 +2079,13 @@ anv_image_msaa_resolve(struct anv_cmd_buffer *cmd_buffer,
get_blorp_surf_for_anv_image(cmd_buffer, src_image, aspect,
VK_IMAGE_USAGE_TRANSFER_SRC_BIT,
ANV_IMAGE_LAYOUT_EXPLICIT_AUX,
src_aux_usage, &src_surf);
if (src_aux_usage == ISL_AUX_USAGE_MCS) {
src_surf.clear_color_addr = anv_to_blorp_address(
anv_image_get_clear_color_addr(cmd_buffer->device, src_image,
VK_IMAGE_ASPECT_COLOR_BIT));
}
src_aux_usage, src_format_override,
&src_surf);
get_blorp_surf_for_anv_image(cmd_buffer, dst_image, aspect,
VK_IMAGE_USAGE_TRANSFER_DST_BIT,
ANV_IMAGE_LAYOUT_EXPLICIT_AUX,
dst_aux_usage, &dst_surf);
dst_aux_usage, dst_format_override,
&dst_surf);
anv_cmd_buffer_mark_image_written(cmd_buffer, dst_image,
aspect, dst_aux_usage,
dst_level, dst_base_layer, layer_count);
@ -2268,7 +2292,7 @@ anv_image_clear_color(struct anv_cmd_buffer *cmd_buffer,
get_blorp_surf_for_anv_image(cmd_buffer, image, aspect,
VK_IMAGE_USAGE_TRANSFER_DST_BIT,
ANV_IMAGE_LAYOUT_EXPLICIT_AUX,
aux_usage, &surf);
aux_usage, format, &surf);
anv_cmd_buffer_mark_image_written(cmd_buffer, image, aspect, aux_usage,
level, base_layer, layer_count);
@ -2305,7 +2329,8 @@ anv_image_clear_depth_stencil(struct anv_cmd_buffer *cmd_buffer,
get_blorp_surf_for_anv_image(cmd_buffer,
image, VK_IMAGE_ASPECT_DEPTH_BIT,
0, ANV_IMAGE_LAYOUT_EXPLICIT_AUX,
depth_aux_usage, &depth);
depth_aux_usage, ISL_FORMAT_UNSUPPORTED,
&depth);
}
struct blorp_surf stencil = {};
@ -2315,7 +2340,8 @@ anv_image_clear_depth_stencil(struct anv_cmd_buffer *cmd_buffer,
get_blorp_surf_for_anv_image(cmd_buffer,
image, VK_IMAGE_ASPECT_STENCIL_BIT,
0, ANV_IMAGE_LAYOUT_EXPLICIT_AUX,
image->planes[plane].aux_usage, &stencil);
image->planes[plane].aux_usage,
ISL_FORMAT_UNSUPPORTED, &stencil);
}
/* Blorp may choose to clear stencil using RGBA32_UINT for better
@ -2369,7 +2395,8 @@ anv_image_hiz_op(struct anv_cmd_buffer *cmd_buffer,
get_blorp_surf_for_anv_image(cmd_buffer,
image, VK_IMAGE_ASPECT_DEPTH_BIT,
0, ANV_IMAGE_LAYOUT_EXPLICIT_AUX,
image->planes[plane].aux_usage, &surf);
image->planes[plane].aux_usage,
ISL_FORMAT_UNSUPPORTED, &surf);
blorp_hiz_op(&batch, &surf, level, base_layer, layer_count, hiz_op);

7
src/intel/vulkan/anv_image.c
View file

@ -645,10 +645,11 @@ add_aux_state_tracking_buffer(struct anv_device *device,
*
* As a result, the state starts 8 bytes lower than where it should be.
*/
assert(device->isl_dev.ss.clear_color_state_size >= 32);
clear_color_state_size = device->isl_dev.ss.clear_color_state_size - 8;
assert(device->isl_dev.ss.clear_color_state_size == 32);
clear_color_state_size = (image->num_view_formats - 1) * 64 + 32 - 8;
} else {
clear_color_state_size = device->isl_dev.ss.clear_value_size;
assert(device->isl_dev.ss.clear_value_size == 16);
clear_color_state_size = image->num_view_formats * 16;
}
/* Clear color and fast clear type */

9
src/intel/vulkan/anv_image_view.c
View file

@ -107,10 +107,8 @@ anv_image_fill_surface_state(struct anv_device *device,
aux_address = anv_image_address(image, &aux_surface->memory_range);
state_inout->aux_address = aux_address;
struct anv_address clear_address = ANV_NULL_ADDRESS;
if (device->info->ver >= 10 && isl_aux_usage_has_fast_clears(aux_usage)) {
clear_address = anv_image_get_clear_color_addr(device, image, aspect);
}
const struct anv_address clear_address =
anv_image_get_clear_color_addr(device, image, view.format, aspect);
state_inout->clear_address = clear_address;
if (image->vk.create_flags & VK_IMAGE_CREATE_PROTECTED_BIT)
@ -125,7 +123,8 @@ anv_image_fill_surface_state(struct anv_device *device,
.aux_usage = aux_usage,
.aux_address = anv_address_physical(aux_address),
.clear_address = anv_address_physical(clear_address),
.use_clear_address = !anv_address_is_null(clear_address),
.use_clear_address =
device->isl_dev.ss.clear_color_state_size > 0,
.mocs = anv_mocs(device, state_inout->address.bo,
view_usage),
.x_offset_sa = tile_x_sa,

40
src/intel/vulkan/anv_private.h
View file

@ -5564,16 +5564,29 @@ anv_image_view_formats_incomplete(const struct anv_image *image);
static inline struct anv_address
anv_image_get_clear_color_addr(UNUSED const struct anv_device *device,
const struct anv_image *image,
enum isl_format view_format,
VkImageAspectFlagBits aspect)
{
assert(image->vk.aspects & (VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV |
VK_IMAGE_ASPECT_DEPTH_BIT));
uint32_t plane = anv_image_aspect_to_plane(image, aspect);
const struct anv_image_memory_range *mem_range =
&image->planes[plane].fast_clear_memory_range;
return anv_image_address(image, mem_range);
const struct anv_address base_addr = anv_image_address(image, mem_range);
if (anv_address_is_null(base_addr))
return ANV_NULL_ADDRESS;
if (view_format == ISL_FORMAT_UNSUPPORTED)
view_format = image->planes[plane].primary_surface.isl.format;
const unsigned clear_state_size = device->info->ver >= 11 ? 64 : 16;
for (int i = 0; i < image->num_view_formats; i++) {
if (view_format == image->view_formats[i]) {
return anv_address_add(base_addr, i * clear_state_size);
}
}
assert(anv_image_view_formats_incomplete(image));
return base_addr;
}
static inline struct anv_address
@ -5584,18 +5597,19 @@ anv_image_get_fast_clear_type_addr(const struct anv_device *device,
/* Xe2+ platforms don't need fast clear type. We shouldn't get here. */
assert(device->info->ver < 20);
struct anv_address addr =
anv_image_get_clear_color_addr(device, image, aspect);
anv_image_get_clear_color_addr(device, image, ISL_FORMAT_UNSUPPORTED,
aspect);
/* Refer to add_aux_state_tracking_buffer(). */
unsigned clear_color_state_size;
if (device->info->ver >= 11) {
/* The fast clear type and the first compression state are stored in the
* last 2 dwords of the clear color struct. Refer to the comment in
* add_aux_state_tracking_buffer().
*/
assert(device->isl_dev.ss.clear_color_state_size >= 32);
clear_color_state_size = device->isl_dev.ss.clear_color_state_size - 8;
} else
clear_color_state_size = device->isl_dev.ss.clear_value_size;
assert(device->isl_dev.ss.clear_color_state_size == 32);
clear_color_state_size = (image->num_view_formats - 1) * 64 + 32 - 8;
} else {
assert(device->isl_dev.ss.clear_value_size == 16);
clear_color_state_size = image->num_view_formats * 16;
}
return anv_address_add(addr, clear_color_state_size);
}

66
src/intel/vulkan/genX_cmd_buffer.c
View file

@ -456,14 +456,14 @@ transition_depth_buffer(struct anv_cmd_buffer *cmd_buffer,
return;
/* Initialize the indirect clear color prior to first use. */
const enum isl_format depth_format =
image->planes[depth_plane].primary_surface.isl.format;
const struct anv_address clear_color_addr =
anv_image_get_clear_color_addr(cmd_buffer->device, image,
anv_image_get_clear_color_addr(cmd_buffer->device, image, depth_format,
VK_IMAGE_ASPECT_DEPTH_BIT);
if (!anv_address_is_null(clear_color_addr) &&
(initial_layout == VK_IMAGE_LAYOUT_UNDEFINED ||
initial_layout == VK_IMAGE_LAYOUT_PREINITIALIZED)) {
const enum isl_format depth_format =
image->planes[depth_plane].primary_surface.isl.format;
const union isl_color_value clear_value =
anv_image_hiz_clear_value(image);
@ -876,6 +876,7 @@ genX(cmd_buffer_load_clear_color)(struct anv_cmd_buffer *cmd_buffer,
});
const struct anv_address entry_addr =
anv_image_get_clear_color_addr(cmd_buffer->device, iview->image,
iview->planes[0].isl.format,
VK_IMAGE_ASPECT_COLOR_BIT);
unsigned copy_size = cmd_buffer->device->isl_dev.ss.clear_value_size;
@ -909,41 +910,38 @@ set_image_clear_color(struct anv_cmd_buffer *cmd_buffer,
const VkImageAspectFlags aspect,
const uint32_t *pixel)
{
UNUSED struct anv_batch *batch = &cmd_buffer->batch;
uint32_t plane = anv_image_aspect_to_plane(image, aspect);
enum isl_format format = image->planes[plane].primary_surface.isl.format;
for (int i = 0; i < image->num_view_formats; i++) {
union isl_color_value clear_color;
isl_color_value_unpack(&clear_color, image->view_formats[i], pixel);
union isl_color_value clear_color;
isl_color_value_unpack(&clear_color, format, pixel);
const struct anv_address addr =
anv_image_get_clear_color_addr(cmd_buffer->device, image,
image->view_formats[i], aspect);
assert(!anv_address_is_null(addr));
struct anv_address addr =
anv_image_get_clear_color_addr(cmd_buffer->device, image, aspect);
assert(!anv_address_is_null(addr));
#if GFX_VER >= 20
assert(cmd_buffer->device->isl_dev.ss.clear_color_state_size == 0);
assert(cmd_buffer->device->isl_dev.ss.clear_value_size == 0);
unreachable("storing clear colors on invalid gfx_ver" );
#elif GFX_VER >= 11
assert(cmd_buffer->device->isl_dev.ss.clear_color_state_size == 32);
uint32_t *dw = anv_batch_emitn(batch, 3 + 6, GENX(MI_STORE_DATA_IMM),
.StoreQword = true, .Address = addr);
dw[3] = clear_color.u32[0];
dw[4] = clear_color.u32[1];
dw[5] = clear_color.u32[2];
dw[6] = clear_color.u32[3];
dw[7] = pixel[0];
dw[8] = pixel[1];
#if GFX_VER >= 11
assert(cmd_buffer->device->isl_dev.ss.clear_color_state_size == 32);
uint32_t *dw = anv_batch_emitn(&cmd_buffer->batch, 3 + 6,
GENX(MI_STORE_DATA_IMM),
.StoreQword = true, .Address = addr);
dw[3] = clear_color.u32[0];
dw[4] = clear_color.u32[1];
dw[5] = clear_color.u32[2];
dw[6] = clear_color.u32[3];
dw[7] = pixel[0];
dw[8] = pixel[1];
#else
assert(cmd_buffer->device->isl_dev.ss.clear_color_state_size == 0);
assert(cmd_buffer->device->isl_dev.ss.clear_value_size == 16);
uint32_t *dw = anv_batch_emitn(batch, 3 + 4, GENX(MI_STORE_DATA_IMM),
.StoreQword = true, .Address = addr);
dw[3] = clear_color.u32[0];
dw[4] = clear_color.u32[1];
dw[5] = clear_color.u32[2];
dw[6] = clear_color.u32[3];
assert(cmd_buffer->device->isl_dev.ss.clear_color_state_size == 0);
assert(cmd_buffer->device->isl_dev.ss.clear_value_size == 16);
uint32_t *dw = anv_batch_emitn(&cmd_buffer->batch, 3 + 4,
GENX(MI_STORE_DATA_IMM),
.StoreQword = true, .Address = addr);
dw[3] = clear_color.u32[0];
dw[4] = clear_color.u32[1];
dw[5] = clear_color.u32[2];
dw[6] = clear_color.u32[3];
#endif
}
}
void