Samuel Pitoiset d2960a8430 radv: consider VK_PIPELINE_STAGE_2_NONE like BOTTOM_OF_PIPE ... VK_PIPELINE_STAGE_2_NONE from sync2 is similar to BOTTOM_OF_PIPE. Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32115>		2024-11-15 08:22:23 +00:00
..
addrlib	ac: make sure VEGA20 and MI200 version ranges don't overlap with other chips	2024-09-27 19:21:55 +00:00
ci	radv/ci: document flakes seen recently	2024-11-13 12:26:49 +00:00
common	radv,ac/nir: split global access using nir_lower_mem_access_bit_sizes	2024-11-13 12:59:26 +00:00
compiler	aco/gfx8: use ds_swizzle_b32 rotate mode	2024-11-14 15:34:48 +00:00
drm-shim	amd/drm-shim: add GFX1150 support	2024-08-13 13:17:17 +00:00
llvm	nir,aco,ac/llvm: add nir_op_alignbyte_amd	2024-11-13 12:59:26 +00:00
registers	amd: add gfx12 register definitions	2024-05-11 22:14:05 -04:00
vpelib	amd/vpelib: remove luma offset (#459)	2024-11-11 13:00:54 +08:00
vulkan	radv: consider VK_PIPELINE_STAGE_2_NONE like BOTTOM_OF_PIPE	2024-11-15 08:22:23 +00:00
meson.build	build: pass licensing information in SPDX form	2024-06-29 12:42:49 -07:00