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e4dadb545f
WAIT takes a notification register as a destination and a src0 argument. Since the same notification register is specified in both fields, we treat it as a special case and disassemble it only once. If we disassemble it as if it is a source register, its scalar region will be printed as <0,1,0>. This causes difficulties round-tripping through the assembler <-> disassembler because that is not an acceptable destination region. If we instead disassemble the destination, we instead get a <1> region which is an acceptable and equivalent region for source and destination. The test .asm files are regenerated by round-tripping them through the assembler/disassembler. Note that the <0> region in the tests was a harmless mistake: the compiler translated it to a <0,1,0> source region and a <1> destination region, since <0> isn't valid. Reviewed-by: Sagar Ghuge <sagar.ghuge@intel.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6543> |
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| .. | ||
| add.asm | ||
| add.expected | ||
| and.asm | ||
| and.expected | ||
| asr.asm | ||
| asr.expected | ||
| bfe.asm | ||
| bfe.expected | ||
| bfi1.asm | ||
| bfi1.expected | ||
| bfi2.asm | ||
| bfi2.expected | ||
| bfrev.asm | ||
| bfrev.expected | ||
| break.asm | ||
| break.expected | ||
| cbit.asm | ||
| cbit.expected | ||
| cmp.asm | ||
| cmp.expected | ||
| cont.asm | ||
| cont.expected | ||
| cr0.asm | ||
| cr0.expected | ||
| csel.asm | ||
| csel.expected | ||
| else.asm | ||
| else.expected | ||
| endif.asm | ||
| endif.expected | ||
| fbh.asm | ||
| fbh.expected | ||
| fbl.asm | ||
| fbl.expected | ||
| frc.asm | ||
| frc.expected | ||
| halt.asm | ||
| halt.expected | ||
| if.asm | ||
| if.expected | ||
| lrp.asm | ||
| lrp.expected | ||
| lzd.asm | ||
| lzd.expected | ||
| mach.asm | ||
| mach.expected | ||
| mad.asm | ||
| mad.expected | ||
| math.asm | ||
| math.expected | ||
| mov.asm | ||
| mov.expected | ||
| mul.asm | ||
| mul.expected | ||
| nop.asm | ||
| nop.expected | ||
| not.asm | ||
| not.expected | ||
| or.asm | ||
| or.expected | ||
| pln.asm | ||
| pln.expected | ||
| rndd.asm | ||
| rndd.expected | ||
| rnde.asm | ||
| rnde.expected | ||
| rndz.asm | ||
| rndz.expected | ||
| sel.asm | ||
| sel.expected | ||
| send.asm | ||
| send.expected | ||
| sendc.asm | ||
| sendc.expected | ||
| shl.asm | ||
| shl.expected | ||
| shr.asm | ||
| shr.expected | ||
| wait.asm | ||
| wait.expected | ||
| while.asm | ||
| while.expected | ||
| xor.asm | ||
| xor.expected | ||