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intel/assembler: Add labels support

Browse source 
Use labels instead of numeric JIP/UIP offsets.
Works for gen6+.

v2:
 - Change asm tests to use labels on gen6+
 - Remove usage of relative offsets on gen6+
 - Consider brw_jump_scale when setting relative offset
 - Return error if there is a JIP/UIP label without matching target
 - Fix matching of label tokens

Signed-off-by: Danylo Piliaiev <danylo.piliaiev@globallogic.com>
Reviewed-by: Sagar Ghuge <sagar.ghuge@intel.com>
Reviewed-by: Matt Turner <mattst88@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4245>
This commit is contained in:
Danylo Piliaiev 2019-06-13 17:26:02 +03:00 • committed by Marge Bot
parent bc4a127d6e
commit 03fbff1efc
70 changed files with 697 additions and 425 deletions
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92
src/intel/tools/i965_asm.c
View file

@ -38,6 +38,9 @@ static enum opt_output_type output_type = OPT_OUTPUT_BIN;
char *input_filename = NULL;
int errors;
struct list_head instr_labels;
struct list_head target_labels;
static void
print_help(const char *progname, FILE *file)
{
@ -119,6 +122,90 @@ i965_disasm_init(uint16_t pci_id)
return devinfo;
}
static bool
i965_postprocess_labels()
{
if (p->devinfo->gen < 6) {
return true;
}
void *store = p->store;
struct target_label *tlabel;
struct instr_label *ilabel, *s;
const unsigned to_bytes_scale = brw_jump_scale(p->devinfo);
LIST_FOR_EACH_ENTRY(tlabel, &target_labels, link) {
LIST_FOR_EACH_ENTRY_SAFE(ilabel, s, &instr_labels, link) {
if (!strcmp(tlabel->name, ilabel->name)) {
brw_inst *inst = store + ilabel->offset;
int relative_offset = (tlabel->offset - ilabel->offset) / sizeof(brw_inst);
relative_offset *= to_bytes_scale;
unsigned opcode = brw_inst_opcode(p->devinfo, inst);
if (ilabel->type == INSTR_LABEL_JIP) {
switch (opcode) {
case BRW_OPCODE_IF:
case BRW_OPCODE_ELSE:
case BRW_OPCODE_ENDIF:
case BRW_OPCODE_WHILE:
if (p->devinfo->gen >= 7) {
brw_inst_set_jip(p->devinfo, inst, relative_offset);
} else if (p->devinfo->gen == 6) {
brw_inst_set_gen6_jump_count(p->devinfo, inst, relative_offset);
}
break;
case BRW_OPCODE_BREAK:
case BRW_OPCODE_HALT:
case BRW_OPCODE_CONTINUE:
brw_inst_set_jip(p->devinfo, inst, relative_offset);
break;
default:
fprintf(stderr, "Unknown opcode %d with JIP label\n", opcode);
return false;
}
} else {
switch (opcode) {
case BRW_OPCODE_IF:
case BRW_OPCODE_ELSE:
if (p->devinfo->gen > 7) {
brw_inst_set_uip(p->devinfo, inst, relative_offset);
} else if (p->devinfo->gen == 7) {
brw_inst_set_uip(p->devinfo, inst, relative_offset);
} else if (p->devinfo->gen == 6) {
// Nothing
}
break;
case BRW_OPCODE_WHILE:
case BRW_OPCODE_ENDIF:
fprintf(stderr, "WHILE/ENDIF cannot have UIP offset\n");
return false;
case BRW_OPCODE_BREAK:
case BRW_OPCODE_CONTINUE:
case BRW_OPCODE_HALT:
brw_inst_set_uip(p->devinfo, inst, relative_offset);
break;
default:
fprintf(stderr, "Unknown opcode %d with UIP label\n", opcode);
return false;
}
}
list_del(&ilabel->link);
}
}
}
LIST_FOR_EACH_ENTRY(ilabel, &instr_labels, link) {
fprintf(stderr, "Unknown label '%s'\n", ilabel->name);
}
return list_is_empty(&instr_labels);
}
int main(int argc, char **argv)
{
char *output_file = NULL;
@ -132,6 +219,8 @@ int main(int argc, char **argv)
struct disasm_info *disasm_info;
struct gen_device_info *devinfo = NULL;
int result = EXIT_FAILURE;
list_inithead(&instr_labels);
list_inithead(&target_labels);
const struct option i965_asm_opts[] = {
{ "help", no_argument, (int *) &help, true },
@ -230,6 +319,9 @@ int main(int argc, char **argv)
if (err || errors)
goto end;
if (!i965_postprocess_labels())
goto end;
store = p->store;
disasm_info = disasm_initialize(p->devinfo, NULL);

24
src/intel/tools/i965_asm.h
View file

@ -35,6 +35,7 @@
#include "compiler/brw_inst.h"
#include "compiler/brw_eu.h"
#include "dev/gen_device_info.h"
#include "util/list.h"
/* glibc < 2.27 defines OVERFLOW in /usr/include/math.h. */
#undef OVERFLOW
@ -48,6 +49,9 @@ extern struct brw_codegen *p;
extern int errors;
extern char *input_filename;
extern struct list_head instr_labels;
extern struct list_head target_labels;
struct condition {
unsigned cond_modifier:4;
unsigned flag_reg_nr:1;
@ -77,4 +81,24 @@ struct options {
unsigned is_compr:1;
};
enum instr_label_type {
INSTR_LABEL_JIP,
INSTR_LABEL_UIP,
};
struct instr_label {
struct list_head link;
char *name;
int offset;
enum instr_label_type type;
};
struct target_label {
struct list_head link;
char *name;
int offset;
};
#endif /* __I965_ASM_H__ */

404
src/intel/tools/i965_gram.y
View file

@ -310,6 +310,22 @@ i965_asm_set_dst_nr(struct brw_codegen *p,
}
}
static void
add_label(struct brw_codegen *p, const char* label_name, enum instr_label_type type)
{
if (!label_name) {
return;
}
struct instr_label *label = rzalloc(p->mem_ctx, struct instr_label);
label->name = ralloc_strdup(p->mem_ctx, label_name);
label->offset = p->next_insn_offset;
label->type = type;
list_addtail(&label->link, &instr_labels);
}
%}
%locations
@ -317,6 +333,7 @@ i965_asm_set_dst_nr(struct brw_codegen *p,
%start ROOT
%union {
char *string;
double number;
int integer;
unsigned long long int llint;
@ -350,6 +367,10 @@ i965_asm_set_dst_nr(struct brw_codegen *p,
%token <integer> TYPE_DF TYPE_NF
%token <integer> TYPE_VF
/* label */
%token <string> JUMP_LABEL
%token <string> JUMP_LABEL_TARGET
/* opcodes */
%token <integer> ADD ADD3 ADDC AND ASR AVG
%token <integer> BFE BFI1 BFI2 BFB BFREV BRC BRD BREAK
@ -502,6 +523,9 @@ i965_asm_set_dst_nr(struct brw_codegen *p,
%type <integer> negate abs chansel math_function sharedfunction
%type <string> jumplabeltarget
%type <string> jumplabel
%code {
static void
@ -608,6 +632,8 @@ instrseq:
| instrseq relocatableinstruction SEMICOLON
| instruction SEMICOLON
| relocatableinstruction SEMICOLON
| instrseq jumplabeltarget
| jumplabeltarget
;
/* Instruction Group */
@ -1072,24 +1098,16 @@ jumpinstruction:
/* branch instruction */
branchinstruction:
predicate ENDIF execsize relativelocation instoptions
predicate ENDIF execsize JUMP_LABEL instoptions
{
add_label(p, $4, INSTR_LABEL_JIP);
brw_next_insn(p, $2);
i965_asm_set_instruction_options(p, $5);
brw_inst_set_exec_size(p->devinfo, brw_last_inst, $3);
if (p->devinfo->gen < 6) {
brw_set_dest(p, brw_last_inst, retype(brw_null_reg(),
BRW_REGISTER_TYPE_D));
brw_set_src0(p, brw_last_inst, retype(brw_null_reg(),
BRW_REGISTER_TYPE_D));
brw_set_src1(p, brw_last_inst, brw_imm_d(0x0));
brw_inst_set_gen4_pop_count(p->devinfo, brw_last_inst,
$4);
} else if (p->devinfo->gen == 6) {
if (p->devinfo->gen == 6) {
brw_set_dest(p, brw_last_inst, brw_imm_w(0x0));
brw_inst_set_gen6_jump_count(p->devinfo, brw_last_inst,
$4);
brw_set_src0(p, brw_last_inst, retype(brw_null_reg(),
BRW_REGISTER_TYPE_D));
brw_set_src1(p, brw_last_inst, retype(brw_null_reg(),
@ -1100,34 +1118,41 @@ branchinstruction:
brw_set_src0(p, brw_last_inst, retype(brw_null_reg(),
BRW_REGISTER_TYPE_D));
brw_set_src1(p, brw_last_inst, brw_imm_w(0x0));
brw_inst_set_jip(p->devinfo, brw_last_inst, $4);
} else {
brw_set_src0(p, brw_last_inst, brw_imm_d($4));
brw_set_src0(p, brw_last_inst, brw_imm_d(0x0));
}
if (p->devinfo->gen < 6)
brw_inst_set_thread_control(p->devinfo, brw_last_inst,
BRW_THREAD_SWITCH);
brw_pop_insn_state(p);
}
| ELSE execsize relativelocation rellocation instoptions
| predicate ENDIF execsize relativelocation instoptions
{
brw_next_insn(p, $2);
i965_asm_set_instruction_options(p, $5);
brw_inst_set_exec_size(p->devinfo, brw_last_inst, $3);
brw_set_dest(p, brw_last_inst, retype(brw_null_reg(),
BRW_REGISTER_TYPE_D));
brw_set_src0(p, brw_last_inst, retype(brw_null_reg(),
BRW_REGISTER_TYPE_D));
brw_set_src1(p, brw_last_inst, brw_imm_d(0x0));
brw_inst_set_gen4_pop_count(p->devinfo, brw_last_inst, $4);
brw_inst_set_thread_control(p->devinfo, brw_last_inst,
BRW_THREAD_SWITCH);
brw_pop_insn_state(p);
}
| ELSE execsize JUMP_LABEL jumplabel instoptions
{
add_label(p, $3, INSTR_LABEL_JIP);
add_label(p, $4, INSTR_LABEL_UIP);
brw_next_insn(p, $1);
i965_asm_set_instruction_options(p, $5);
brw_inst_set_exec_size(p->devinfo, brw_last_inst, $2);
if (p->devinfo->gen < 6) {
brw_set_dest(p, brw_last_inst, brw_ip_reg());
brw_set_src0(p, brw_last_inst, brw_ip_reg());
brw_set_src1(p, brw_last_inst, brw_imm_d(0x0));
brw_inst_set_gen4_jump_count(p->devinfo, brw_last_inst,
$3);
brw_inst_set_gen4_pop_count(p->devinfo, brw_last_inst,
$4);
} else if (p->devinfo->gen == 6) {
if (p->devinfo->gen == 6) {
brw_set_dest(p, brw_last_inst, brw_imm_w(0x0));
brw_inst_set_gen6_jump_count(p->devinfo, brw_last_inst,
$3);
brw_set_src0(p, brw_last_inst, retype(brw_null_reg(),
BRW_REGISTER_TYPE_D));
brw_set_src1(p, brw_last_inst, retype(brw_null_reg(),
@ -1137,39 +1162,41 @@ branchinstruction:
BRW_REGISTER_TYPE_D));
brw_set_src0(p, brw_last_inst, retype(brw_null_reg(),
BRW_REGISTER_TYPE_D));
brw_set_src1(p, brw_last_inst, brw_imm_w($3));
brw_inst_set_jip(p->devinfo, brw_last_inst, $3);
brw_inst_set_uip(p->devinfo, brw_last_inst, $4);
brw_set_src1(p, brw_last_inst, brw_imm_w(0));
} else {
brw_set_dest(p, brw_last_inst, retype(brw_null_reg(),
BRW_REGISTER_TYPE_D));
brw_set_src0(p, brw_last_inst, brw_imm_d($3));
brw_inst_set_jip(p->devinfo, brw_last_inst, $3);
brw_inst_set_uip(p->devinfo, brw_last_inst, $4);
if (p->devinfo->gen < 12)
brw_set_src0(p, brw_last_inst, brw_imm_d(0));
}
}
| ELSE execsize relativelocation rellocation instoptions
{
brw_next_insn(p, $1);
i965_asm_set_instruction_options(p, $5);
brw_inst_set_exec_size(p->devinfo, brw_last_inst, $2);
if (!p->single_program_flow && p->devinfo->gen < 6)
brw_set_dest(p, brw_last_inst, brw_ip_reg());
brw_set_src0(p, brw_last_inst, brw_ip_reg());
brw_set_src1(p, brw_last_inst, brw_imm_d(0x0));
brw_inst_set_gen4_jump_count(p->devinfo, brw_last_inst, $3);
brw_inst_set_gen4_pop_count(p->devinfo, brw_last_inst, $4);
if (!p->single_program_flow)
brw_inst_set_thread_control(p->devinfo, brw_last_inst,
BRW_THREAD_SWITCH);
}
| predicate IF execsize relativelocation rellocation instoptions
| predicate IF execsize JUMP_LABEL jumplabel instoptions
{
add_label(p, $4, INSTR_LABEL_JIP);
add_label(p, $5, INSTR_LABEL_UIP);
brw_next_insn(p, $2);
i965_asm_set_instruction_options(p, $6);
brw_inst_set_exec_size(p->devinfo, brw_last_inst, $3);
if (p->devinfo->gen < 6) {
brw_set_dest(p, brw_last_inst, brw_ip_reg());
brw_set_src0(p, brw_last_inst, brw_ip_reg());
brw_set_src1(p, brw_last_inst, brw_imm_d(0x0));
brw_inst_set_gen4_jump_count(p->devinfo, brw_last_inst,
$4);
brw_inst_set_gen4_pop_count(p->devinfo, brw_last_inst,
$5);
} else if (p->devinfo->gen == 6) {
if (p->devinfo->gen == 6) {
brw_set_dest(p, brw_last_inst, brw_imm_w(0x0));
brw_inst_set_gen6_jump_count(p->devinfo, brw_last_inst,
$4);
brw_set_src0(p, brw_last_inst,
vec1(retype(brw_null_reg(),
BRW_REGISTER_TYPE_D)));
@ -1183,64 +1210,80 @@ branchinstruction:
brw_set_src0(p, brw_last_inst,
vec1(retype(brw_null_reg(),
BRW_REGISTER_TYPE_D)));
brw_set_src1(p, brw_last_inst, brw_imm_w($4));
brw_inst_set_jip(p->devinfo, brw_last_inst, $4);
brw_inst_set_uip(p->devinfo, brw_last_inst, $5);
brw_set_src1(p, brw_last_inst, brw_imm_w(0x0));
} else {
brw_set_dest(p, brw_last_inst,
vec1(retype(brw_null_reg(),
BRW_REGISTER_TYPE_D)));
brw_set_src0(p, brw_last_inst, brw_imm_d($4));
brw_inst_set_jip(p->devinfo, brw_last_inst, $4);
brw_inst_set_uip(p->devinfo, brw_last_inst, $5);
if (p->devinfo->gen < 12)
brw_set_src0(p, brw_last_inst, brw_imm_d(0x0));
}
if (!p->single_program_flow && p->devinfo->gen < 6)
brw_pop_insn_state(p);
}
| predicate IF execsize relativelocation rellocation instoptions
{
brw_next_insn(p, $2);
i965_asm_set_instruction_options(p, $6);
brw_inst_set_exec_size(p->devinfo, brw_last_inst, $3);
brw_set_dest(p, brw_last_inst, brw_ip_reg());
brw_set_src0(p, brw_last_inst, brw_ip_reg());
brw_set_src1(p, brw_last_inst, brw_imm_d(0x0));
brw_inst_set_gen4_jump_count(p->devinfo, brw_last_inst, $4);
brw_inst_set_gen4_pop_count(p->devinfo, brw_last_inst, $5);
if (!p->single_program_flow)
brw_inst_set_thread_control(p->devinfo, brw_last_inst,
BRW_THREAD_SWITCH);
brw_pop_insn_state(p);
}
| predicate IFF execsize JUMP_LABEL instoptions
{
add_label(p, $4, INSTR_LABEL_JIP);
brw_next_insn(p, $2);
i965_asm_set_instruction_options(p, $5);
brw_inst_set_exec_size(p->devinfo, brw_last_inst, $3);
if (p->devinfo->gen == 6) {
brw_set_src0(p, brw_last_inst,
vec1(retype(brw_null_reg(),
BRW_REGISTER_TYPE_D)));
brw_set_src1(p, brw_last_inst,
vec1(retype(brw_null_reg(),
BRW_REGISTER_TYPE_D)));
} else if (p->devinfo->gen == 7) {
brw_set_dest(p, brw_last_inst,
vec1(retype(brw_null_reg(),
BRW_REGISTER_TYPE_D)));
brw_set_src0(p, brw_last_inst,
vec1(retype(brw_null_reg(),
BRW_REGISTER_TYPE_D)));
brw_set_src1(p, brw_last_inst, brw_imm_w(0x0));
} else {
brw_set_dest(p, brw_last_inst,
vec1(retype(brw_null_reg(),
BRW_REGISTER_TYPE_D)));
if (p->devinfo->gen < 12)
brw_set_src0(p, brw_last_inst, brw_imm_d(0x0));
}
brw_pop_insn_state(p);
}
| predicate IFF execsize relativelocation instoptions
{
brw_next_insn(p, $2);
i965_asm_set_instruction_options(p, $5);
brw_inst_set_exec_size(p->devinfo, brw_last_inst, $3);
if (p->devinfo->gen < 6) {
brw_set_dest(p, brw_last_inst, brw_ip_reg());
brw_set_src0(p, brw_last_inst, brw_ip_reg());
brw_inst_set_gen4_jump_count(p->devinfo, brw_last_inst,
$4);
brw_set_src1(p, brw_last_inst, brw_imm_d($4));
} else if (p->devinfo->gen == 6) {
brw_set_dest(p, brw_last_inst, brw_imm_w($4));
brw_inst_set_gen6_jump_count(p->devinfo, brw_last_inst,
$4);
brw_set_src0(p, brw_last_inst,
vec1(retype(brw_null_reg(),
BRW_REGISTER_TYPE_D)));
brw_set_src1(p, brw_last_inst,
vec1(retype(brw_null_reg(),
BRW_REGISTER_TYPE_D)));
} else if (p->devinfo->gen == 7) {
brw_set_dest(p, brw_last_inst,
vec1(retype(brw_null_reg(),
BRW_REGISTER_TYPE_D)));
brw_set_src0(p, brw_last_inst,
vec1(retype(brw_null_reg(),
BRW_REGISTER_TYPE_D)));
brw_set_src1(p, brw_last_inst, brw_imm_w($4));
brw_inst_set_jip(p->devinfo, brw_last_inst, $4);
} else {
brw_set_dest(p, brw_last_inst,
vec1(retype(brw_null_reg(),
BRW_REGISTER_TYPE_D)));
brw_set_src0(p, brw_last_inst, brw_imm_d($4));
brw_inst_set_jip(p->devinfo, brw_last_inst, $4);
}
brw_set_dest(p, brw_last_inst, brw_ip_reg());
brw_set_src0(p, brw_last_inst, brw_ip_reg());
brw_inst_set_gen4_jump_count(p->devinfo, brw_last_inst, $4);
brw_set_src1(p, brw_last_inst, brw_imm_d($4));
if (!p->single_program_flow && p->devinfo->gen < 6)
if (!p->single_program_flow)
brw_inst_set_thread_control(p->devinfo, brw_last_inst,
BRW_THREAD_SWITCH);
@ -1250,8 +1293,11 @@ branchinstruction:
/* break instruction */
breakinstruction:
predicate BREAK execsize relativelocation relativelocation instoptions
predicate BREAK execsize JUMP_LABEL JUMP_LABEL instoptions
{
add_label(p, $4, INSTR_LABEL_JIP);
add_label(p, $5, INSTR_LABEL_UIP);
brw_next_insn(p, $2);
i965_asm_set_instruction_options(p, $6);
brw_inst_set_exec_size(p->devinfo, brw_last_inst, $3);
@ -1259,47 +1305,70 @@ breakinstruction:
if (p->devinfo->gen >= 8) {
brw_set_dest(p, brw_last_inst, retype(brw_null_reg(),
BRW_REGISTER_TYPE_D));
brw_set_src0(p, brw_last_inst, brw_imm_d($4));
brw_inst_set_uip(p->devinfo, brw_last_inst, $5);
} else if (p->devinfo->gen >= 6) {
brw_set_src0(p, brw_last_inst, brw_imm_d(0x0));
} else {
brw_set_dest(p, brw_last_inst, retype(brw_null_reg(),
BRW_REGISTER_TYPE_D));
brw_set_src0(p, brw_last_inst, retype(brw_null_reg(),
BRW_REGISTER_TYPE_D));
brw_set_src1(p, brw_last_inst, brw_imm_d(0x0));
brw_inst_set_jip(p->devinfo, brw_last_inst, $4);
brw_inst_set_uip(p->devinfo, brw_last_inst, $5);
} else {
brw_set_dest(p, brw_last_inst, brw_ip_reg());
brw_set_src0(p, brw_last_inst, brw_ip_reg());
brw_set_src1(p, brw_last_inst, brw_imm_d(0x0));
brw_inst_set_gen4_jump_count(p->devinfo, brw_last_inst,
$4);
brw_inst_set_gen4_pop_count(p->devinfo, brw_last_inst,
$5);
}
brw_pop_insn_state(p);
}
| predicate HALT execsize relativelocation relativelocation instoptions
| predicate BREAK execsize relativelocation relativelocation instoptions
{
brw_next_insn(p, $2);
i965_asm_set_instruction_options(p, $6);
brw_inst_set_exec_size(p->devinfo, brw_last_inst, $3);
brw_set_dest(p, brw_last_inst, brw_ip_reg());
brw_set_src0(p, brw_last_inst, brw_ip_reg());
brw_set_src1(p, brw_last_inst, brw_imm_d(0x0));
brw_inst_set_gen4_jump_count(p->devinfo, brw_last_inst, $4);
brw_inst_set_gen4_pop_count(p->devinfo, brw_last_inst, $5);
brw_pop_insn_state(p);
}
| predicate HALT execsize JUMP_LABEL JUMP_LABEL instoptions
{
add_label(p, $4, INSTR_LABEL_JIP);
add_label(p, $5, INSTR_LABEL_UIP);
brw_next_insn(p, $2);
i965_asm_set_instruction_options(p, $6);
brw_inst_set_exec_size(p->devinfo, brw_last_inst, $3);
brw_set_dest(p, brw_last_inst, retype(brw_null_reg(),
BRW_REGISTER_TYPE_D));
if (p->devinfo->gen >= 8) {
brw_set_src0(p, brw_last_inst, brw_imm_d($4));
brw_inst_set_uip(p->devinfo, brw_last_inst, $5);
brw_set_src0(p, brw_last_inst, brw_imm_d(0x0));
} else {
brw_set_src0(p, brw_last_inst, retype(brw_null_reg(),
BRW_REGISTER_TYPE_D));
brw_set_src1(p, brw_last_inst, brw_imm_d($5));
brw_set_src1(p, brw_last_inst, brw_imm_d(0x0));
}
brw_pop_insn_state(p);
}
| predicate CONT execsize JUMP_LABEL JUMP_LABEL instoptions
{
add_label(p, $4, INSTR_LABEL_JIP);
add_label(p, $5, INSTR_LABEL_UIP);
brw_next_insn(p, $2);
i965_asm_set_instruction_options(p, $6);
brw_inst_set_exec_size(p->devinfo, brw_last_inst, $3);
brw_set_dest(p, brw_last_inst, brw_ip_reg());
if (p->devinfo->gen >= 8) {
brw_set_src0(p, brw_last_inst, brw_imm_d(0x0));
} else {
brw_set_src0(p, brw_last_inst, brw_ip_reg());
brw_set_src1(p, brw_last_inst, brw_imm_d(0x0));
}
brw_inst_set_jip(p->devinfo, brw_last_inst, $4);
brw_inst_set_uip(p->devinfo, brw_last_inst, $5);
brw_pop_insn_state(p);
}
| predicate CONT execsize relativelocation relativelocation instoptions
@ -1309,23 +1378,11 @@ breakinstruction:
brw_inst_set_exec_size(p->devinfo, brw_last_inst, $3);
brw_set_dest(p, brw_last_inst, brw_ip_reg());
if (p->devinfo->gen >= 8) {
brw_set_src0(p, brw_last_inst, brw_imm_d(0x0));
brw_inst_set_jip(p->devinfo, brw_last_inst, $4);
brw_inst_set_uip(p->devinfo, brw_last_inst, $5);
} else {
brw_set_src0(p, brw_last_inst, brw_ip_reg());
brw_set_src1(p, brw_last_inst, brw_imm_d(0x0));
if (p->devinfo->gen >= 6) {
brw_inst_set_jip(p->devinfo, brw_last_inst, $4);
brw_inst_set_uip(p->devinfo, brw_last_inst, $5);
} else {
brw_inst_set_gen4_jump_count(p->devinfo, brw_last_inst,
$4);
brw_inst_set_gen4_pop_count(p->devinfo, brw_last_inst,
$5);
}
}
brw_set_src0(p, brw_last_inst, brw_ip_reg());
brw_set_src1(p, brw_last_inst, brw_imm_d(0x0));
brw_inst_set_gen4_jump_count(p->devinfo, brw_last_inst, $4);
brw_inst_set_gen4_pop_count(p->devinfo, brw_last_inst, $5);
brw_pop_insn_state(p);
}
@ -1333,50 +1390,52 @@ breakinstruction:
/* loop instruction */
loopinstruction:
predicate WHILE execsize relativelocation instoptions
predicate WHILE execsize JUMP_LABEL instoptions
{
add_label(p, $4, INSTR_LABEL_JIP);
brw_next_insn(p, $2);
i965_asm_set_instruction_options(p, $5);
brw_inst_set_exec_size(p->devinfo, brw_last_inst, $3);
if (p->devinfo->gen >= 8) {
brw_set_dest(p, brw_last_inst,
retype(brw_null_reg(),
BRW_REGISTER_TYPE_D));
brw_set_src0(p, brw_last_inst, brw_imm_d(0x0));
} else if (p->devinfo->gen == 7) {
brw_set_dest(p, brw_last_inst,
retype(brw_null_reg(),
BRW_REGISTER_TYPE_D));
brw_set_src0(p, brw_last_inst,
retype(brw_null_reg(),
BRW_REGISTER_TYPE_D));
brw_set_src1(p, brw_last_inst,
brw_imm_w(0x0));
} else {
brw_set_dest(p, brw_last_inst, brw_imm_w(0x0));
brw_set_src0(p, brw_last_inst,
retype(brw_null_reg(),
BRW_REGISTER_TYPE_D));
brw_set_src1(p, brw_last_inst,
retype(brw_null_reg(),
BRW_REGISTER_TYPE_D));
}
brw_pop_insn_state(p);
}
| predicate WHILE execsize relativelocation instoptions
{
brw_next_insn(p, $2);
i965_asm_set_instruction_options(p, $5);
brw_inst_set_exec_size(p->devinfo, brw_last_inst, $3);
if (p->devinfo->gen >= 6) {
if (p->devinfo->gen >= 8) {
brw_set_dest(p, brw_last_inst,
retype(brw_null_reg(),
BRW_REGISTER_TYPE_D));
brw_set_src0(p, brw_last_inst, brw_imm_d($4));
} else if (p->devinfo->gen == 7) {
brw_set_dest(p, brw_last_inst,
retype(brw_null_reg(),
BRW_REGISTER_TYPE_D));
brw_set_src0(p, brw_last_inst,
retype(brw_null_reg(),
BRW_REGISTER_TYPE_D));
brw_set_src1(p, brw_last_inst,
brw_imm_w(0x0));
brw_inst_set_jip(p->devinfo, brw_last_inst,
$4);
} else {
brw_set_dest(p, brw_last_inst, brw_imm_w(0x0));
brw_inst_set_gen6_jump_count(p->devinfo,
brw_last_inst,
$4);
brw_set_src0(p, brw_last_inst,
retype(brw_null_reg(),
BRW_REGISTER_TYPE_D));
brw_set_src1(p, brw_last_inst,
retype(brw_null_reg(),
BRW_REGISTER_TYPE_D));
}
} else {
brw_set_dest(p, brw_last_inst, brw_ip_reg());
brw_set_src0(p, brw_last_inst, brw_ip_reg());
brw_set_src1(p, brw_last_inst, brw_imm_d(0x0));
brw_inst_set_gen4_jump_count(p->devinfo, brw_last_inst,
$4);
brw_inst_set_gen4_pop_count(p->devinfo, brw_last_inst,
0);
}
brw_set_dest(p, brw_last_inst, brw_ip_reg());
brw_set_src0(p, brw_last_inst, brw_ip_reg());
brw_set_src1(p, brw_last_inst, brw_imm_d(0x0));
brw_inst_set_gen4_jump_count(p->devinfo, brw_last_inst, $4);
brw_inst_set_gen4_pop_count(p->devinfo, brw_last_inst, 0);
brw_pop_insn_state(p);
}
| DO execsize instoptions
@ -1419,6 +1478,23 @@ relativelocation:
}
;
jumplabel:
JUMP_LABEL { $$ = $1; }
| %empty { $$ = NULL; }
;
jumplabeltarget:
JUMP_LABEL_TARGET
{
struct target_label *label = rzalloc(p->mem_ctx, struct target_label);
label->name = ralloc_strdup(p->mem_ctx, $1);
label->offset = p->next_insn_offset;
list_addtail(&label->link, &target_labels);
}
;
/* Destination register */
dst:
dstoperand

20
src/intel/tools/i965_lex.l
View file

@ -24,6 +24,7 @@ extern char *input_filename;
%x CHANNEL
%x REG
%x DOTSEL
%x LABEL
%%
/* eat up single line comment */
@ -367,8 +368,8 @@ sr[0-9]+ { yylval.integer = atoi(yytext + 2); return STATEREG; }
/* Eat up JIP and UIP token, their values will be parsed
* in numeric section
*/
"JIP: " { }
"UIP: " { }
"JIP: " { BEGIN(LABEL); }
"UIP: " { BEGIN(LABEL); }
"Jump: " { }
"Pop: " { }
[ \t]+ { }
@ -383,6 +384,21 @@ sr[0-9]+ { yylval.integer = atoi(yytext + 2); return STATEREG; }
return LONG;
}
/* jump label target */
[a-zA-Z_][0-9a-zA-Z_]*":" {
yylval.string = ralloc_strdup(p->mem_ctx, yytext);
/* Stomp the trailing ':' */
yylval.string[yyleng - 1] = '\0';
return JUMP_LABEL_TARGET;
}
/* jump label */
<LABEL>[a-zA-Z_][0-9a-zA-Z_]* {
yylval.string = ralloc_strdup(p->mem_ctx, yytext);
BEGIN(INITIAL);
return JUMP_LABEL;
}
\n { yycolumn = 1; }
. {

15
src/intel/tools/tests/gen6/break.asm
View file

@ -1,6 +1,9 @@
break(8) JIP: 2 UIP: 12 { align16 1Q };
break(8) JIP: 2 UIP: 104 { align1 1Q };
break(16) JIP: 2 UIP: 104 { align1 1H };
(+f0.0) break(8) JIP: 4 UIP: 12 { align1 1Q };
(+f0.0) break(16) JIP: 4 UIP: 12 { align1 1H };
(+f0.0.x) break(8) JIP: 122 UIP: 124 { align16 1Q };
break(8) JIP: LABEL1 UIP: LABEL2 { align16 1Q };
LABEL1:
break(8) JIP: LABEL2 UIP: LABEL2 { align1 1Q };
break(16) JIP: LABEL2 UIP: LABEL2 { align1 1H };
LABEL2:
(+f0.0) break(8) JIP: LABEL3 UIP: LABEL3 { align1 1Q };
(+f0.0) break(16) JIP: LABEL3 UIP: LABEL3 { align1 1H };
(+f0.0.x) break(8) JIP: LABEL3 UIP: LABEL3 { align16 1Q };
LABEL3:

12
src/intel/tools/tests/gen6/break.expected
View file

@ -1,6 +1,6 @@
28 01 60 00 84 1c 0f 20 04 00 6e 00 02 00 0c 00
28 00 60 00 84 1c 00 20 00 00 8d 00 02 00 68 00
28 00 80 00 84 1c 00 20 00 00 8d 00 02 00 68 00
28 00 61 00 84 1c 00 20 00 00 8d 00 04 00 0c 00
28 00 81 00 84 1c 00 20 00 00 8d 00 04 00 0c 00
28 01 62 00 84 1c 0f 20 04 00 6e 00 7a 00 7c 00
28 01 60 00 84 1c 0f 20 04 00 6e 00 02 00 06 00
28 00 60 00 84 1c 00 20 00 00 8d 00 04 00 04 00
28 00 80 00 84 1c 00 20 00 00 8d 00 02 00 02 00
28 00 61 00 84 1c 00 20 00 00 8d 00 06 00 06 00
28 00 81 00 84 1c 00 20 00 00 8d 00 04 00 04 00
28 01 62 00 84 1c 0f 20 04 00 6e 00 02 00 02 00

9
src/intel/tools/tests/gen6/cont.asm
View file

@ -1,3 +1,6 @@
cont(8) JIP: 2 UIP: 8 { align1 1Q };
cont(16) JIP: 2 UIP: 8 { align1 1H };
cont(8) JIP: 2 UIP: 8 { align16 1Q };
cont(8) JIP: LABEL0 UIP: LABEL2 { align1 1Q };
LABEL0:
cont(16) JIP: LABEL1 UIP: LABEL2 { align1 1H };
LABEL1:
cont(8) JIP: LABEL2 UIP: LABEL2 { align16 1Q };
LABEL2:

6
src/intel/tools/tests/gen6/cont.expected
View file

@ -1,3 +1,3 @@
29 00 60 00 00 1c 00 34 00 14 60 00 02 00 08 00
29 00 80 00 00 1c 00 34 00 14 60 00 02 00 08 00
29 01 60 00 00 1c 0f 34 04 14 6e 00 02 00 08 00
29 00 60 00 00 1c 00 34 00 14 60 00 02 00 06 00
29 00 80 00 00 1c 00 34 00 14 60 00 02 00 04 00
29 01 60 00 00 1c 0f 34 04 14 6e 00 02 00 02 00

7
src/intel/tools/tests/gen6/else.asm
View file

@ -1,3 +1,4 @@
else(8) JIP: 12 { align1 1Q };
else(16) JIP: 12 { align1 1H };
else(8) JIP: 18 { align16 1Q };
else(8) JIP: LABEL0 { align1 1Q };
else(16) JIP: LABEL0 { align1 1H };
else(8) JIP: LABEL0 { align16 1Q };
LABEL0:

6
src/intel/tools/tests/gen6/else.expected
View file

@ -1,3 +1,3 @@
24 00 60 00 8f 10 0c 00 00 00 8d 00 00 00 8d 00
24 00 80 00 8f 10 0c 00 00 00 8d 00 00 00 8d 00
24 01 60 00 8f 10 12 00 04 00 6e 00 04 00 6e 00
24 00 60 00 8f 10 06 00 00 00 8d 00 00 00 8d 00
24 00 80 00 8f 10 04 00 00 00 8d 00 00 00 8d 00
24 01 60 00 8f 10 02 00 04 00 6e 00 04 00 6e 00

9
src/intel/tools/tests/gen6/endif.asm
View file

@ -1,3 +1,6 @@
endif(8) JIP: 2 { align16 1Q };
endif(8) JIP: 2 { align1 1Q };
endif(16) JIP: 2 { align1 1H };
endif(8) JIP: LABEL1 { align16 1Q };
LABEL1:
endif(8) JIP: LABEL2 { align1 1Q };
LABEL2:
endif(16) JIP: LABEL3 { align1 1H };
LABEL3:

10
src/intel/tools/tests/gen6/halt.asm
View file

@ -1,4 +1,6 @@
(-f0.1.any4h) halt(8) JIP: 96 UIP: 98 { align1 1Q };
halt(8) JIP: 2 UIP: 2 { align1 1Q };
(-f0.1.any4h) halt(16) JIP: 100 UIP: 102 { align1 1H };
halt(16) JIP: 2 UIP: 2 { align1 1H };
(-f0.1.any4h) halt(8) JIP: LABEL0 UIP: LABEL0 { align1 1Q };
halt(8) JIP: LABEL1 UIP: LABEL1 { align1 1Q };
LABEL1:
(-f0.1.any4h) halt(16) JIP: LABEL0 UIP: LABEL0 { align1 1H };
halt(16) JIP: LABEL0 UIP: LABEL0 { align1 1H };
LABEL0:

4
src/intel/tools/tests/gen6/halt.expected
View file

@ -1,4 +1,4 @@
2a 00 76 00 84 1c 00 20 00 00 8d 02 60 00 62 00
2a 00 76 00 84 1c 00 20 00 00 8d 02 08 00 08 00
2a 00 60 00 84 1c 00 20 00 00 8d 00 02 00 02 00
2a 00 96 00 84 1c 00 20 00 00 8d 02 64 00 66 00
2a 00 96 00 84 1c 00 20 00 00 8d 02 04 00 04 00
2a 00 80 00 84 1c 00 20 00 00 8d 00 02 00 02 00

14
src/intel/tools/tests/gen6/if.asm
View file

@ -1,6 +1,8 @@
(+f0.0) if(8) JIP: 84 { align16 1Q };
(+f0.0) if(8) JIP: 32 { align1 1Q };
(+f0.0) if(16) JIP: 32 { align1 1H };
(+f0.0.x) if(8) JIP: 18 { align16 1Q };
(-f0.0) if(8) JIP: 12 { align1 1Q };
(-f0.0) if(16) JIP: 12 { align1 1H };
(+f0.0) if(8) JIP: LABEL0 { align16 1Q };
LABEL0:
(+f0.0) if(8) JIP: LABEL1 { align1 1Q };
(+f0.0) if(16) JIP: LABEL1 { align1 1H };
(+f0.0.x) if(8) JIP: LABEL1 { align16 1Q };
(-f0.0) if(8) JIP: LABEL1 { align1 1Q };
(-f0.0) if(16) JIP: LABEL1 { align1 1H };
LABEL1:

12
src/intel/tools/tests/gen6/if.expected
View file

@ -1,6 +1,6 @@
22 01 61 00 8f 10 54 00 04 00 0e 00 04 00 0e 00
22 00 61 00 8f 10 20 00 00 00 00 00 00 00 00 00
22 00 81 00 8f 10 20 00 00 00 00 00 00 00 00 00
22 01 62 00 8f 10 12 00 04 00 0e 00 04 00 0e 00
22 00 71 00 8f 10 0c 00 00 00 00 00 00 00 00 00
22 00 91 00 8f 10 0c 00 00 00 00 00 00 00 00 00
22 01 61 00 8f 10 02 00 04 00 0e 00 04 00 0e 00
22 00 61 00 8f 10 0a 00 00 00 00 00 00 00 00 00
22 00 81 00 8f 10 08 00 00 00 00 00 00 00 00 00
22 01 62 00 8f 10 06 00 04 00 0e 00 04 00 0e 00
22 00 71 00 8f 10 04 00 00 00 00 00 00 00 00 00
22 00 91 00 8f 10 02 00 00 00 00 00 00 00 00 00

13
src/intel/tools/tests/gen6/while.asm
View file

@ -1,6 +1,7 @@
while(8) JIP: -76 { align16 1Q };
while(8) JIP: -108 { align1 1Q };
while(16) JIP: -108 { align1 1H };
(-f0.0) while(8) JIP: -48 { align1 1Q };
(-f0.0) while(16) JIP: -48 { align1 1H };
(-f0.0.x) while(8) JIP: -48 { align16 1Q };
LABEL0:
while(8) JIP: LABEL0 { align16 1Q };
while(8) JIP: LABEL0 { align1 1Q };
while(16) JIP: LABEL0 { align1 1H };
(-f0.0) while(8) JIP: LABEL0 { align1 1Q };
(-f0.0) while(16) JIP: LABEL0 { align1 1H };
(-f0.0.x) while(8) JIP: LABEL0 { align16 1Q };

12
src/intel/tools/tests/gen6/while.expected
View file

@ -1,6 +1,6 @@
27 01 60 00 8f 10 b4 ff 04 00 6e 00 04 00 6e 00
27 00 60 00 8f 10 94 ff 00 00 8d 00 00 00 8d 00
27 00 80 00 8f 10 94 ff 00 00 8d 00 00 00 8d 00
27 00 71 00 8f 10 d0 ff 00 00 8d 00 00 00 8d 00
27 00 91 00 8f 10 d0 ff 00 00 8d 00 00 00 8d 00
27 01 72 00 8f 10 d0 ff 04 00 6e 00 04 00 6e 00
27 01 60 00 8f 10 00 00 04 00 6e 00 04 00 6e 00
27 00 60 00 8f 10 fe ff 00 00 8d 00 00 00 8d 00
27 00 80 00 8f 10 fc ff 00 00 8d 00 00 00 8d 00
27 00 71 00 8f 10 fa ff 00 00 8d 00 00 00 8d 00
27 00 91 00 8f 10 f8 ff 00 00 8d 00 00 00 8d 00
27 01 72 00 8f 10 f6 ff 04 00 6e 00 04 00 6e 00

14
src/intel/tools/tests/gen7.5/break.asm
View file

@ -1,6 +1,8 @@
break(8) JIP: 2 UIP: 8 { align1 1Q };
break(16) JIP: 2 UIP: 8 { align1 1H };
break(8) JIP: 2 UIP: 10 { align16 1Q };
(+f0.0) break(8) JIP: 4 UIP: 10 { align1 1Q };
(+f0.0) break(16) JIP: 4 UIP: 10 { align1 1H };
(+f0.0.x) break(8) JIP: 110 UIP: 110 { align16 1Q };
break(8) JIP: LABEL0 UIP: LABEL1 { align1 1Q };
break(16) JIP: LABEL0 UIP: LABEL1 { align1 1H };
break(8) JIP: LABEL0 UIP: LABEL1 { align16 1Q };
LABEL0:
(+f0.0) break(8) JIP: LABEL1 UIP: LABEL1 { align1 1Q };
(+f0.0) break(16) JIP: LABEL1 UIP: LABEL1 { align1 1H };
(+f0.0.x) break(8) JIP: LABEL1 UIP: LABEL1 { align16 1Q };
LABEL1:

12
src/intel/tools/tests/gen7.5/break.expected
View file

@ -1,6 +1,6 @@
28 00 60 00 84 1c 00 20 00 00 8d 00 02 00 08 00
28 00 80 00 84 1c 00 20 00 00 8d 00 02 00 08 00
28 01 60 00 84 1c 0f 20 04 00 6e 00 02 00 0a 00
28 00 61 00 84 1c 00 20 00 00 8d 00 04 00 0a 00
28 00 81 00 84 1c 00 20 00 00 8d 00 04 00 0a 00
28 01 62 00 84 1c 0f 20 04 00 6e 00 6e 00 6e 00
28 00 60 00 84 1c 00 20 00 00 8d 00 06 00 0c 00
28 00 80 00 84 1c 00 20 00 00 8d 00 04 00 0a 00
28 01 60 00 84 1c 0f 20 04 00 6e 00 02 00 08 00
28 00 61 00 84 1c 00 20 00 00 8d 00 06 00 06 00
28 00 81 00 84 1c 00 20 00 00 8d 00 04 00 04 00
28 01 62 00 84 1c 0f 20 04 00 6e 00 02 00 02 00

9
src/intel/tools/tests/gen7.5/cont.asm
View file

@ -1,3 +1,6 @@
cont(8) JIP: 2 UIP: 8 { align1 1Q };
cont(16) JIP: 2 UIP: 8 { align1 1H };
cont(8) JIP: 2 UIP: 8 { align16 1Q };
cont(8) JIP: LABEL0 UIP: LABEL2 { align1 1Q };
LABEL0:
cont(16) JIP: LABEL1 UIP: LABEL2 { align1 1H };
LABEL1:
cont(8) JIP: LABEL2 UIP: LABEL2 { align16 1Q };
LABEL2:

6
src/intel/tools/tests/gen7.5/cont.expected
View file

@ -1,3 +1,3 @@
29 00 60 00 00 1c 00 34 00 14 60 00 02 00 08 00
29 00 80 00 00 1c 00 34 00 14 60 00 02 00 08 00
29 01 60 00 00 1c 0f 34 04 14 6e 00 02 00 08 00
29 00 60 00 00 1c 00 34 00 14 60 00 02 00 06 00
29 00 80 00 00 1c 00 34 00 14 60 00 02 00 04 00
29 01 60 00 00 1c 0f 34 04 14 6e 00 02 00 02 00

7
src/intel/tools/tests/gen7.5/else.asm
View file

@ -1,3 +1,4 @@
else(8) JIP: 4 { align16 1Q };
else(8) JIP: 72 { align1 1Q };
else(16) JIP: 72 { align1 1H };
else(8) JIP: LABEL0 { align16 1Q };
else(8) JIP: LABEL0 { align1 1Q };
else(16) JIP: LABEL0 { align1 1H };
LABEL0:

6
src/intel/tools/tests/gen7.5/else.expected
View file

@ -1,3 +1,3 @@
24 01 60 00 84 3c 0f 20 04 00 6e 00 04 00 00 00
24 00 60 00 84 3c 00 20 00 00 8d 00 48 00 00 00
24 00 80 00 84 3c 00 20 00 00 8d 00 48 00 00 00
24 01 60 00 84 3c 0f 20 04 00 6e 00 06 00 00 00
24 00 60 00 84 3c 00 20 00 00 8d 00 04 00 00 00
24 00 80 00 84 3c 00 20 00 00 8d 00 02 00 00 00

8
src/intel/tools/tests/gen7.5/endif.asm
View file

@ -1,3 +1,5 @@
endif(8) JIP: 6 { align1 1Q };
endif(16) JIP: 6 { align1 1H };
endif(8) JIP: 2 { align16 1Q };
endif(8) JIP: LABEL0 { align1 1Q };
LABEL0:
endif(16) JIP: LABEL1 { align1 1H };
endif(8) JIP: LABEL1 { align16 1Q };
LABEL1:

4
src/intel/tools/tests/gen7.5/endif.expected
View file

@ -1,3 +1,3 @@
25 00 60 00 84 3c 00 20 00 00 8d 00 06 00 00 00
25 00 80 00 84 3c 00 20 00 00 8d 00 06 00 00 00
25 00 60 00 84 3c 00 20 00 00 8d 00 02 00 00 00
25 00 80 00 84 3c 00 20 00 00 8d 00 04 00 00 00
25 01 60 00 84 3c 0f 20 04 00 6e 00 02 00 00 00

10
src/intel/tools/tests/gen7.5/halt.asm
View file

@ -1,4 +1,6 @@
(-f0.1.any4h) halt(8) JIP: 72 UIP: 74 { align1 1Q };
halt(8) JIP: 2 UIP: 2 { align1 1Q };
(-f0.1.any4h) halt(16) JIP: 72 UIP: 74 { align1 1H };
halt(16) JIP: 2 UIP: 2 { align1 1H };
(-f0.1.any4h) halt(8) JIP: LABEL0 UIP: LABEL0 { align1 1Q };
halt(8) JIP: LABEL1 UIP: LABEL1 { align1 1Q };
LABEL1:
(-f0.1.any4h) halt(16) JIP: LABEL0 UIP: LABEL0 { align1 1H };
halt(16) JIP: LABEL0 UIP: LABEL0 { align1 1H };
LABEL0:

4
src/intel/tools/tests/gen7.5/halt.expected
View file

@ -1,4 +1,4 @@
2a 00 76 00 84 1c 00 20 00 00 8d 02 48 00 4a 00
2a 00 76 00 84 1c 00 20 00 00 8d 02 08 00 08 00
2a 00 60 00 84 1c 00 20 00 00 8d 00 02 00 02 00
2a 00 96 00 84 1c 00 20 00 00 8d 02 48 00 4a 00
2a 00 96 00 84 1c 00 20 00 00 8d 02 04 00 04 00
2a 00 80 00 84 1c 00 20 00 00 8d 00 02 00 02 00

15
src/intel/tools/tests/gen7.5/if.asm
View file

@ -1,6 +1,9 @@
(-f0.0) if(8) JIP: 8 UIP: 8 { align1 1Q };
(-f0.0) if(16) JIP: 8 UIP: 8 { align1 1H };
(+f0.0.x) if(8) JIP: 18 UIP: 18 { align16 1Q };
(+f0.0) if(8) JIP: 14 UIP: 14 { align16 1Q };
(+f0.0) if(8) JIP: 12 UIP: 82 { align1 1Q };
(+f0.0) if(16) JIP: 12 UIP: 82 { align1 1H };
(-f0.0) if(8) JIP: LABEL0 UIP: LABEL2 { align1 1Q };
LABEL0:
(-f0.0) if(16) JIP: LABEL2 UIP: LABEL1 { align1 1H };
(+f0.0.x) if(8) JIP: LABEL2 UIP: LABEL1 { align16 1Q };
LABEL1:
(+f0.0) if(8) JIP: LABEL2 UIP: LABEL2 { align16 1Q };
(+f0.0) if(8) JIP: LABEL2 UIP: LABEL2 { align1 1Q };
(+f0.0) if(16) JIP: LABEL2 UIP: LABEL2 { align1 1H };
LABEL2:

12
src/intel/tools/tests/gen7.5/if.expected
View file

@ -1,6 +1,6 @@
22 00 71 00 84 3c 00 20 00 00 00 00 08 00 08 00
22 00 91 00 84 3c 00 20 00 00 00 00 08 00 08 00
22 01 62 00 84 3c 0f 20 04 00 0e 00 12 00 12 00
22 01 61 00 84 3c 0f 20 04 00 0e 00 0e 00 0e 00
22 00 61 00 84 3c 00 20 00 00 00 00 0c 00 52 00
22 00 81 00 84 3c 00 20 00 00 00 00 0c 00 52 00
22 00 71 00 84 3c 00 20 00 00 00 00 02 00 0c 00
22 00 91 00 84 3c 00 20 00 00 00 00 0a 00 04 00
22 01 62 00 84 3c 0f 20 04 00 0e 00 08 00 02 00
22 01 61 00 84 3c 0f 20 04 00 0e 00 06 00 06 00
22 00 61 00 84 3c 00 20 00 00 00 00 04 00 04 00
22 00 81 00 84 3c 00 20 00 00 00 00 02 00 02 00

13
src/intel/tools/tests/gen7.5/while.asm
View file

@ -1,6 +1,7 @@
while(8) JIP: -20 { align1 1Q };
while(16) JIP: -20 { align1 1H };
while(8) JIP: -30 { align16 1Q };
(-f0.0) while(8) JIP: -48 { align1 1Q };
(-f0.0) while(16) JIP: -48 { align1 1H };
(-f0.0.x) while(8) JIP: -48 { align16 1Q };
LABEL0:
while(8) JIP: LABEL0 { align1 1Q };
while(16) JIP: LABEL0 { align1 1H };
while(8) JIP: LABEL0 { align16 1Q };
(-f0.0) while(8) JIP: LABEL0 { align1 1Q };
(-f0.0) while(16) JIP: LABEL0 { align1 1H };
(-f0.0.x) while(8) JIP: LABEL0 { align16 1Q };

12
src/intel/tools/tests/gen7.5/while.expected
View file

@ -1,6 +1,6 @@
27 00 60 00 84 3c 00 20 00 00 8d 00 ec ff 00 00
27 00 80 00 84 3c 00 20 00 00 8d 00 ec ff 00 00
27 01 60 00 84 3c 0f 20 04 00 6e 00 e2 ff 00 00
27 00 71 00 84 3c 00 20 00 00 8d 00 d0 ff 00 00
27 00 91 00 84 3c 00 20 00 00 8d 00 d0 ff 00 00
27 01 72 00 84 3c 0f 20 04 00 6e 00 d0 ff 00 00
27 00 60 00 84 3c 00 20 00 00 8d 00 00 00 00 00
27 00 80 00 84 3c 00 20 00 00 8d 00 fe ff 00 00
27 01 60 00 84 3c 0f 20 04 00 6e 00 fc ff 00 00
27 00 71 00 84 3c 00 20 00 00 8d 00 fa ff 00 00
27 00 91 00 84 3c 00 20 00 00 8d 00 f8 ff 00 00
27 01 72 00 84 3c 0f 20 04 00 6e 00 f6 ff 00 00

15
src/intel/tools/tests/gen7/break.asm
View file

@ -1,6 +1,9 @@
break(8) JIP: 2 UIP: 40 { align1 1Q };
break(16) JIP: 2 UIP: 48 { align1 1H };
(+f0.0.x) break(8) JIP: 110 UIP: 110 { align16 1Q };
(+f0.0) break(8) JIP: 2 UIP: 12 { align1 1Q };
(+f0.0) break(16) JIP: 2 UIP: 12 { align1 1H };
break(8) JIP: 2 UIP: 38 { align16 1Q };
break(8) JIP: LABEL0 UIP: LABEL0 { align1 1Q };
LABEL0:
break(16) JIP: LABEL1 UIP: LABEL2 { align1 1H };
(+f0.0.x) break(8) JIP: LABEL1 UIP: LABEL2 { align16 1Q };
LABEL1:
(+f0.0) break(8) JIP: LABEL2 UIP: LABEL2 { align1 1Q };
(+f0.0) break(16) JIP: LABEL2 UIP: LABEL2 { align1 1H };
break(8) JIP: LABEL2 UIP: LABEL2 { align16 1Q };
LABEL2:

12
src/intel/tools/tests/gen7/break.expected
View file

@ -1,6 +1,6 @@
28 00 60 00 84 1c 00 20 00 00 8d 00 02 00 28 00
28 00 80 00 84 1c 00 20 00 00 8d 00 02 00 30 00
28 01 62 00 84 1c 0f 20 04 00 6e 00 6e 00 6e 00
28 00 61 00 84 1c 00 20 00 00 8d 00 02 00 0c 00
28 00 81 00 84 1c 00 20 00 00 8d 00 02 00 0c 00
28 01 60 00 84 1c 0f 20 04 00 6e 00 02 00 26 00
28 00 60 00 84 1c 00 20 00 00 8d 00 02 00 02 00
28 00 80 00 84 1c 00 20 00 00 8d 00 04 00 0a 00
28 01 62 00 84 1c 0f 20 04 00 6e 00 02 00 08 00
28 00 61 00 84 1c 00 20 00 00 8d 00 06 00 06 00
28 00 81 00 84 1c 00 20 00 00 8d 00 04 00 04 00
28 01 60 00 84 1c 0f 20 04 00 6e 00 02 00 02 00

7
src/intel/tools/tests/gen7/else.asm
View file

@ -1,3 +1,4 @@
else(8) JIP: 12 { align1 1Q };
else(16) JIP: 12 { align1 1H };
else(8) JIP: 18 { align16 1Q };
else(8) JIP: LABEL0 { align1 1Q };
else(16) JIP: LABEL0 { align1 1H };
else(8) JIP: LABEL0 { align16 1Q };
LABEL0:

6
src/intel/tools/tests/gen7/else.expected
View file

@ -1,3 +1,3 @@
24 00 60 00 84 3c 00 20 00 00 8d 00 0c 00 00 00
24 00 80 00 84 3c 00 20 00 00 8d 00 0c 00 00 00
24 01 60 00 84 3c 0f 20 04 00 6e 00 12 00 00 00
24 00 60 00 84 3c 00 20 00 00 8d 00 06 00 00 00
24 00 80 00 84 3c 00 20 00 00 8d 00 04 00 00 00
24 01 60 00 84 3c 0f 20 04 00 6e 00 02 00 00 00

9
src/intel/tools/tests/gen7/endif.asm
View file

@ -1,3 +1,6 @@
endif(8) JIP: 2 { align16 1Q };
endif(8) JIP: 2 { align1 1Q };
endif(16) JIP: 2 { align1 1H };
endif(8) JIP: LABEL1 { align16 1Q };
LABEL1:
endif(8) JIP: LABEL2 { align1 1Q };
LABEL2:
endif(16) JIP: LABEL3 { align1 1H };
LABEL3:

10
src/intel/tools/tests/gen7/halt.asm
View file

@ -1,4 +1,6 @@
(-f0.1.any4h) halt(8) JIP: 72 UIP: 74 { align1 1Q };
halt(8) JIP: 2 UIP: 2 { align1 1Q };
(-f0.1.any4h) halt(16) JIP: 76 UIP: 78 { align1 1H };
halt(16) JIP: 2 UIP: 2 { align1 1H };
(-f0.1.any4h) halt(8) JIP: LABEL0 UIP: LABEL0 { align1 1Q };
halt(8) JIP: LABEL1 UIP: LABEL1 { align1 1Q };
LABEL1:
(-f0.1.any4h) halt(16) JIP: LABEL0 UIP: LABEL0 { align1 1H };
halt(16) JIP: LABEL0 UIP: LABEL0 { align1 1H };
LABEL0:

4
src/intel/tools/tests/gen7/halt.expected
View file

@ -1,4 +1,4 @@
2a 00 76 00 84 1c 00 20 00 00 8d 02 48 00 4a 00
2a 00 76 00 84 1c 00 20 00 00 8d 02 08 00 08 00
2a 00 60 00 84 1c 00 20 00 00 8d 00 02 00 02 00
2a 00 96 00 84 1c 00 20 00 00 8d 02 4c 00 4e 00
2a 00 96 00 84 1c 00 20 00 00 8d 02 04 00 04 00
2a 00 80 00 84 1c 00 20 00 00 8d 00 02 00 02 00

15
src/intel/tools/tests/gen7/if.asm
View file

@ -1,6 +1,9 @@
(+f0.0.x) if(8) JIP: 18 UIP: 18 { align16 1Q };
(+f0.0) if(8) JIP: 14 UIP: 14 { align16 1Q };
(+f0.0) if(8) JIP: 32 UIP: 96 { align1 1Q };
(+f0.0) if(16) JIP: 32 UIP: 96 { align1 1H };
(-f0.0) if(8) JIP: 10 UIP: 10 { align1 1Q };
(-f0.0) if(16) JIP: 10 UIP: 10 { align1 1H };
(+f0.0.x) if(8) JIP: LABEL0 UIP: LABEL2 { align16 1Q };
LABEL0:
(+f0.0) if(8) JIP: LABEL2 UIP: LABEL1 { align16 1Q };
(+f0.0) if(8) JIP: LABEL2 UIP: LABEL1 { align1 1Q };
LABEL1:
(+f0.0) if(16) JIP: LABEL2 UIP: LABEL2 { align1 1H };
(-f0.0) if(8) JIP: LABEL2 UIP: LABEL2 { align1 1Q };
(-f0.0) if(16) JIP: LABEL2 UIP: LABEL2 { align1 1H };
LABEL2:

12
src/intel/tools/tests/gen7/if.expected
View file

@ -1,6 +1,6 @@
22 01 62 00 84 3c 0f 20 04 00 0e 00 12 00 12 00
22 01 61 00 84 3c 0f 20 04 00 0e 00 0e 00 0e 00
22 00 61 00 84 3c 00 20 00 00 00 00 20 00 60 00
22 00 81 00 84 3c 00 20 00 00 00 00 20 00 60 00
22 00 71 00 84 3c 00 20 00 00 00 00 0a 00 0a 00
22 00 91 00 84 3c 00 20 00 00 00 00 0a 00 0a 00
22 01 62 00 84 3c 0f 20 04 00 0e 00 02 00 0c 00
22 01 61 00 84 3c 0f 20 04 00 0e 00 0a 00 04 00
22 00 61 00 84 3c 00 20 00 00 00 00 08 00 02 00
22 00 81 00 84 3c 00 20 00 00 00 00 06 00 06 00
22 00 71 00 84 3c 00 20 00 00 00 00 04 00 04 00
22 00 91 00 84 3c 00 20 00 00 00 00 02 00 02 00

11
src/intel/tools/tests/gen7/while.asm
View file

@ -1,5 +1,6 @@
while(8) JIP: -50 { align1 1Q };
while(16) JIP: -58 { align1 1H };
while(8) JIP: -8 { align16 1Q };
(-f0.0) while(8) JIP: -10 { align1 1Q };
(-f0.0) while(16) JIP: -10 { align1 1H };
LABEL0:
while(8) JIP: LABEL0 { align1 1Q };
while(16) JIP: LABEL0 { align1 1H };
while(8) JIP: LABEL0 { align16 1Q };
(-f0.0) while(8) JIP: LABEL0 { align1 1Q };
(-f0.0) while(16) JIP: LABEL0 { align1 1H };

10
src/intel/tools/tests/gen7/while.expected
View file

@ -1,5 +1,5 @@
27 00 60 00 84 3c 00 20 00 00 8d 00 ce ff 00 00
27 00 80 00 84 3c 00 20 00 00 8d 00 c6 ff 00 00
27 01 60 00 84 3c 0f 20 04 00 6e 00 f8 ff 00 00
27 00 71 00 84 3c 00 20 00 00 8d 00 f6 ff 00 00
27 00 91 00 84 3c 00 20 00 00 8d 00 f6 ff 00 00
27 00 60 00 84 3c 00 20 00 00 8d 00 00 00 00 00
27 00 80 00 84 3c 00 20 00 00 8d 00 fe ff 00 00
27 01 60 00 84 3c 0f 20 04 00 6e 00 fc ff 00 00
27 00 71 00 84 3c 00 20 00 00 8d 00 fa ff 00 00
27 00 91 00 84 3c 00 20 00 00 8d 00 f8 ff 00 00

10
src/intel/tools/tests/gen8/break.asm
View file

@ -1,4 +1,6 @@
break(8) JIP: 16 UIP: 64 { align1 1Q };
break(16) JIP: 16 UIP: 64 { align1 1H };
(+f0.0) break(8) JIP: 32 UIP: 80 { align1 1Q };
(+f0.0) break(16) JIP: 32 UIP: 80 { align1 1H };
break(8) JIP: LABEL0 UIP: LABEL1 { align1 1Q };
break(16) JIP: LABEL0 UIP: LABEL1 { align1 1H };
LABEL0:
(+f0.0) break(8) JIP: LABEL1 UIP: LABEL1 { align1 1Q };
(+f0.0) break(16) JIP: LABEL1 UIP: LABEL1 { align1 1H };
LABEL1:

8
src/intel/tools/tests/gen8/break.expected
View file

@ -1,4 +1,4 @@
28 00 60 00 20 0e 00 20 40 00 00 00 10 00 00 00
28 00 80 00 20 0e 00 20 40 00 00 00 10 00 00 00
28 00 61 00 20 0e 00 20 50 00 00 00 20 00 00 00
28 00 81 00 20 0e 00 20 50 00 00 00 20 00 00 00
28 00 60 00 20 0e 00 20 40 00 00 00 20 00 00 00
28 00 80 00 20 0e 00 20 30 00 00 00 10 00 00 00
28 00 61 00 20 0e 00 20 20 00 00 00 20 00 00 00
28 00 81 00 20 0e 00 20 10 00 00 00 10 00 00 00

6
src/intel/tools/tests/gen8/cont.asm
View file

@ -1,2 +1,4 @@
cont(8) JIP: 16 UIP: 64 { align1 1Q };
cont(16) JIP: 16 UIP: 64 { align1 1H };
cont(8) JIP: LABEL0 UIP: LABEL1 { align1 1Q };
LABEL0:
cont(16) JIP: LABEL1 UIP: LABEL1 { align1 1H };
LABEL1:

4
src/intel/tools/tests/gen8/cont.expected
View file

@ -1,2 +1,2 @@
29 00 60 00 00 0e 00 34 40 00 00 00 10 00 00 00
29 00 80 00 00 0e 00 34 40 00 00 00 10 00 00 00
29 00 60 00 00 0e 00 34 20 00 00 00 10 00 00 00
29 00 80 00 00 0e 00 34 10 00 00 00 10 00 00 00

7
src/intel/tools/tests/gen8/else.asm
View file

@ -1,3 +1,4 @@
else(8) JIP: 288 UIP: 288 { align1 1Q };
else(16) JIP: 240 UIP: 240 { align1 1H };
else(32) JIP: 144 UIP: 144 { align1 };
else(8) JIP: LABEL0 UIP: LABEL0 { align1 1Q };
else(16) JIP: LABEL0 UIP: LABEL0 { align1 1H };
else(32) JIP: LABEL0 UIP: LABEL0 { align1 };
LABEL0:

6
src/intel/tools/tests/gen8/else.expected
View file

@ -1,3 +1,3 @@
24 00 60 00 20 0e 00 20 20 01 00 00 20 01 00 00
24 00 80 00 20 0e 00 20 f0 00 00 00 f0 00 00 00
24 00 a0 00 20 0e 00 20 90 00 00 00 90 00 00 00
24 00 60 00 20 0e 00 20 30 00 00 00 30 00 00 00
24 00 80 00 20 0e 00 20 20 00 00 00 20 00 00 00
24 00 a0 00 20 0e 00 20 10 00 00 00 10 00 00 00

7
src/intel/tools/tests/gen8/endif.asm
View file

@ -1,3 +1,4 @@
endif(8) JIP: 80 { align1 1Q };
endif(16) JIP: 48 { align1 1H };
endif(32) JIP: 16 { align1 };
endif(8) JIP: LABEL0 { align1 1Q };
endif(16) JIP: LABEL0 { align1 1H };
endif(32) JIP: LABEL0 { align1 };
LABEL0:

4
src/intel/tools/tests/gen8/endif.expected
View file

@ -1,3 +1,3 @@
25 00 60 00 00 0e 00 00 00 00 00 08 50 00 00 00
25 00 80 00 00 0e 00 00 00 00 00 08 30 00 00 00
25 00 60 00 00 0e 00 00 00 00 00 08 30 00 00 00
25 00 80 00 00 0e 00 00 00 00 00 08 20 00 00 00
25 00 a0 00 00 0e 00 00 00 00 00 08 10 00 00 00

10
src/intel/tools/tests/gen8/halt.asm
View file

@ -1,4 +1,6 @@
(-f0.1.any4h) halt(8) JIP: 176 UIP: 192 { align1 1Q };
halt(8) JIP: 16 UIP: 16 { align1 1Q };
(-f0.1.any4h) halt(16) JIP: 176 UIP: 192 { align1 1H };
halt(16) JIP: 16 UIP: 16 { align1 1H };
(-f0.1.any4h) halt(8) JIP: LABEL0 UIP: LABEL0 { align1 1Q };
halt(8) JIP: LABEL1 UIP: LABEL1 { align1 1Q };
LABEL1:
(-f0.1.any4h) halt(16) JIP: LABEL0 UIP: LABEL0 { align1 1H };
halt(16) JIP: LABEL0 UIP: LABEL0 { align1 1H };
LABEL0:

4
src/intel/tools/tests/gen8/halt.expected
View file

@ -1,4 +1,4 @@
2a 00 76 00 21 0e 00 20 c0 00 00 00 b0 00 00 00
2a 00 76 00 21 0e 00 20 40 00 00 00 40 00 00 00
2a 00 60 00 20 0e 00 20 10 00 00 00 10 00 00 00
2a 00 96 00 21 0e 00 20 c0 00 00 00 b0 00 00 00
2a 00 96 00 21 0e 00 20 20 00 00 00 20 00 00 00
2a 00 80 00 20 0e 00 20 10 00 00 00 10 00 00 00

12
src/intel/tools/tests/gen8/if.asm
View file

@ -1,5 +1,7 @@
(+f0.0) if(8) JIP: 1376 UIP: 1392 { align1 1Q };
(-f0.0) if(8) JIP: 4704 UIP: 4704 { align1 1Q };
(-f0.0) if(16) JIP: 64 UIP: 64 { align1 1H };
(+f0.0) if(16) JIP: 96 UIP: 320 { align1 1H };
(+f0.0) if(32) JIP: 80 UIP: 80 { align1 };
(+f0.0) if(8) JIP: LABEL0 UIP: LABEL1 { align1 1Q };
(-f0.0) if(8) JIP: LABEL0 UIP: LABEL1 { align1 1Q };
LABEL0:
(-f0.0) if(16) JIP: LABEL1 UIP: LABEL1 { align1 1H };
(+f0.0) if(16) JIP: LABEL1 UIP: LABEL1 { align1 1H };
(+f0.0) if(32) JIP: LABEL1 UIP: LABEL1 { align1 };
LABEL1:

10
src/intel/tools/tests/gen8/if.expected
View file

@ -1,5 +1,5 @@
22 00 61 00 20 0e 00 20 70 05 00 00 60 05 00 00
22 00 71 00 20 0e 00 20 60 12 00 00 60 12 00 00
22 00 91 00 20 0e 00 20 40 00 00 00 40 00 00 00
22 00 81 00 20 0e 00 20 40 01 00 00 60 00 00 00
22 00 a1 00 20 0e 00 20 50 00 00 00 50 00 00 00
22 00 61 00 20 0e 00 20 50 00 00 00 20 00 00 00
22 00 71 00 20 0e 00 20 40 00 00 00 10 00 00 00
22 00 91 00 20 0e 00 20 30 00 00 00 30 00 00 00
22 00 81 00 20 0e 00 20 20 00 00 00 20 00 00 00
22 00 a1 00 20 0e 00 20 10 00 00 00 10 00 00 00

9
src/intel/tools/tests/gen8/while.asm
View file

@ -1,4 +1,5 @@
while(8) JIP: -160 { align1 1Q };
while(16) JIP: -160 { align1 1H };
(-f0.0) while(8) JIP: -384 { align1 1Q };
(-f0.0) while(16) JIP: -384 { align1 1H };
LABEL0:
while(8) JIP: LABEL0 { align1 1Q };
while(16) JIP: LABEL0 { align1 1H };
(-f0.0) while(8) JIP: LABEL0 { align1 1Q };
(-f0.0) while(16) JIP: LABEL0 { align1 1H };

8
src/intel/tools/tests/gen8/while.expected
View file

@ -1,4 +1,4 @@
27 00 60 00 20 0e 00 20 00 00 00 08 60 ff ff ff
27 00 80 00 20 0e 00 20 00 00 00 08 60 ff ff ff
27 00 71 00 20 0e 00 20 00 00 00 08 80 fe ff ff
27 00 91 00 20 0e 00 20 00 00 00 08 80 fe ff ff
27 00 60 00 20 0e 00 20 00 00 00 08 00 00 00 00
27 00 80 00 20 0e 00 20 00 00 00 08 f0 ff ff ff
27 00 71 00 20 0e 00 20 00 00 00 08 e0 ff ff ff
27 00 91 00 20 0e 00 20 00 00 00 08 d0 ff ff ff

10
src/intel/tools/tests/gen9/break.asm
View file

@ -1,4 +1,6 @@
break(8) JIP: 16 UIP: 64 { align1 1Q };
break(16) JIP: 16 UIP: 64 { align1 1H };
(+f0.0) break(8) JIP: 32 UIP: 80 { align1 1Q };
(+f0.0) break(16) JIP: 32 UIP: 80 { align1 1H };
break(8) JIP: LABEL0 UIP: LABEL1 { align1 1Q };
break(16) JIP: LABEL0 UIP: LABEL1 { align1 1H };
LABEL0:
(+f0.0) break(8) JIP: LABEL1 UIP: LABEL1 { align1 1Q };
(+f0.0) break(16) JIP: LABEL1 UIP: LABEL1 { align1 1H };
LABEL1:

8
src/intel/tools/tests/gen9/break.expected
View file

@ -1,4 +1,4 @@
28 00 60 00 20 0e 00 20 40 00 00 00 10 00 00 00
28 00 80 00 20 0e 00 20 40 00 00 00 10 00 00 00
28 00 61 00 20 0e 00 20 50 00 00 00 20 00 00 00
28 00 81 00 20 0e 00 20 50 00 00 00 20 00 00 00
28 00 60 00 20 0e 00 20 40 00 00 00 20 00 00 00
28 00 80 00 20 0e 00 20 30 00 00 00 10 00 00 00
28 00 61 00 20 0e 00 20 20 00 00 00 20 00 00 00
28 00 81 00 20 0e 00 20 10 00 00 00 10 00 00 00

6
src/intel/tools/tests/gen9/cont.asm
View file

@ -1,2 +1,4 @@
cont(8) JIP: 16 UIP: 64 { align1 1Q };
cont(16) JIP: 16 UIP: 64 { align1 1H };
cont(8) JIP: LABEL0 UIP: LABEL1 { align1 1Q };
LABEL0:
cont(16) JIP: LABEL1 UIP: LABEL1 { align1 1H };
LABEL1:

4
src/intel/tools/tests/gen9/cont.expected
View file

@ -1,2 +1,2 @@
29 00 60 00 00 0e 00 34 40 00 00 00 10 00 00 00
29 00 80 00 00 0e 00 34 40 00 00 00 10 00 00 00
29 00 60 00 00 0e 00 34 20 00 00 00 10 00 00 00
29 00 80 00 00 0e 00 34 10 00 00 00 10 00 00 00

7
src/intel/tools/tests/gen9/else.asm
View file

@ -1,3 +1,4 @@
else(8) JIP: 288 UIP: 288 { align1 1Q };
else(16) JIP: 240 UIP: 240 { align1 1H };
else(32) JIP: 272 UIP: 272 { align1 };
else(8) JIP: LABEL0 UIP: LABEL0 { align1 1Q };
else(16) JIP: LABEL0 UIP: LABEL0 { align1 1H };
else(32) JIP: LABEL0 UIP: LABEL0 { align1 };
LABEL0:

6
src/intel/tools/tests/gen9/else.expected
View file

@ -1,3 +1,3 @@
24 00 60 00 20 0e 00 20 20 01 00 00 20 01 00 00
24 00 80 00 20 0e 00 20 f0 00 00 00 f0 00 00 00
24 00 a0 00 20 0e 00 20 10 01 00 00 10 01 00 00
24 00 60 00 20 0e 00 20 30 00 00 00 30 00 00 00
24 00 80 00 20 0e 00 20 20 00 00 00 20 00 00 00
24 00 a0 00 20 0e 00 20 10 00 00 00 10 00 00 00

7
src/intel/tools/tests/gen9/endif.asm
View file

@ -1,3 +1,4 @@
endif(8) JIP: 80 { align1 1Q };
endif(16) JIP: 48 { align1 1H };
endif(32) JIP: 16 { align1 };
endif(8) JIP: LABEL0 { align1 1Q };
endif(16) JIP: LABEL0 { align1 1H };
endif(32) JIP: LABEL0 { align1 };
LABEL0:

4
src/intel/tools/tests/gen9/endif.expected
View file

@ -1,3 +1,3 @@
25 00 60 00 00 0e 00 00 00 00 00 08 50 00 00 00
25 00 80 00 00 0e 00 00 00 00 00 08 30 00 00 00
25 00 60 00 00 0e 00 00 00 00 00 08 30 00 00 00
25 00 80 00 00 0e 00 00 00 00 00 08 20 00 00 00
25 00 a0 00 00 0e 00 00 00 00 00 08 10 00 00 00

10
src/intel/tools/tests/gen9/halt.asm
View file

@ -1,4 +1,6 @@
(-f0.1.any4h) halt(8) JIP: 176 UIP: 192 { align1 1Q };
halt(8) JIP: 16 UIP: 16 { align1 1Q };
(-f0.1.any4h) halt(16) JIP: 176 UIP: 192 { align1 1H };
halt(16) JIP: 16 UIP: 16 { align1 1H };
(-f0.1.any4h) halt(8) JIP: LABEL0 UIP: LABEL0 { align1 1Q };
halt(8) JIP: LABEL1 UIP: LABEL1 { align1 1Q };
LABEL1:
(-f0.1.any4h) halt(16) JIP: LABEL0 UIP: LABEL0 { align1 1H };
halt(16) JIP: LABEL0 UIP: LABEL0 { align1 1H };
LABEL0:

4
src/intel/tools/tests/gen9/halt.expected
View file

@ -1,4 +1,4 @@
2a 00 76 00 21 0e 00 20 c0 00 00 00 b0 00 00 00
2a 00 76 00 21 0e 00 20 40 00 00 00 40 00 00 00
2a 00 60 00 20 0e 00 20 10 00 00 00 10 00 00 00
2a 00 96 00 21 0e 00 20 c0 00 00 00 b0 00 00 00
2a 00 96 00 21 0e 00 20 20 00 00 00 20 00 00 00
2a 00 80 00 20 0e 00 20 10 00 00 00 10 00 00 00

12
src/intel/tools/tests/gen9/if.asm
View file

@ -1,5 +1,7 @@
(+f0.0) if(8) JIP: 1376 UIP: 1392 { align1 1Q };
(-f0.0) if(8) JIP: 4704 UIP: 4704 { align1 1Q };
(-f0.0) if(16) JIP: 64 UIP: 64 { align1 1H };
(+f0.0) if(16) JIP: 96 UIP: 320 { align1 1H };
(+f0.0) if(32) JIP: 80 UIP: 80 { align1 };
(+f0.0) if(8) JIP: LABEL0 UIP: LABEL1 { align1 1Q };
(-f0.0) if(8) JIP: LABEL0 UIP: LABEL1 { align1 1Q };
LABEL0:
(-f0.0) if(16) JIP: LABEL1 UIP: LABEL1 { align1 1H };
(+f0.0) if(16) JIP: LABEL1 UIP: LABEL1 { align1 1H };
(+f0.0) if(32) JIP: LABEL1 UIP: LABEL1 { align1 };
LABEL1:

10
src/intel/tools/tests/gen9/if.expected
View file

@ -1,5 +1,5 @@
22 00 61 00 20 0e 00 20 70 05 00 00 60 05 00 00
22 00 71 00 20 0e 00 20 60 12 00 00 60 12 00 00
22 00 91 00 20 0e 00 20 40 00 00 00 40 00 00 00
22 00 81 00 20 0e 00 20 40 01 00 00 60 00 00 00
22 00 a1 00 20 0e 00 20 50 00 00 00 50 00 00 00
22 00 61 00 20 0e 00 20 50 00 00 00 20 00 00 00
22 00 71 00 20 0e 00 20 40 00 00 00 10 00 00 00
22 00 91 00 20 0e 00 20 30 00 00 00 30 00 00 00
22 00 81 00 20 0e 00 20 20 00 00 00 20 00 00 00
22 00 a1 00 20 0e 00 20 10 00 00 00 10 00 00 00

9
src/intel/tools/tests/gen9/while.asm
View file

@ -1,4 +1,5 @@
while(8) JIP: -160 { align1 1Q };
while(16) JIP: -160 { align1 1H };
(-f0.0) while(8) JIP: -384 { align1 1Q };
(-f0.0) while(16) JIP: -384 { align1 1H };
LABEL0:
while(8) JIP: LABEL0 { align1 1Q };
while(16) JIP: LABEL0 { align1 1H };
(-f0.0) while(8) JIP: LABEL0 { align1 1Q };
(-f0.0) while(16) JIP: LABEL0 { align1 1H };

8
src/intel/tools/tests/gen9/while.expected
View file

@ -1,4 +1,4 @@
27 00 60 00 20 0e 00 20 00 00 00 08 60 ff ff ff
27 00 80 00 20 0e 00 20 00 00 00 08 60 ff ff ff
27 00 71 00 20 0e 00 20 00 00 00 08 80 fe ff ff
27 00 91 00 20 0e 00 20 00 00 00 08 80 fe ff ff
27 00 60 00 20 0e 00 20 00 00 00 08 00 00 00 00
27 00 80 00 20 0e 00 20 00 00 00 08 f0 ff ff ff
27 00 71 00 20 0e 00 20 00 00 00 08 e0 ff ff ff
27 00 91 00 20 0e 00 20 00 00 00 08 d0 ff ff ff