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1ae8ac35c0
Make pseudo instructions for the IR separate from real Bifrost and Valhall instructions, which are kept in their own ISA.xml files. Reviewed-by: Mary Guillemard <mary.guillemard@collabora.com> Acked-by: Boris Brezillon <boris.brezillon@collabora.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30179>
195 lines
5.9 KiB
XML
195 lines
5.9 KiB
XML
<!--
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Copyright (C) 2024 Collabora Ltd.
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Permission is hereby granted, free of charge, to any person obtaining a
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copy of this software and associated documentation files (the "Software"),
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to deal in the Software without restriction, including without limitation
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the rights to use, copy, modify, merge, publish, distribute, sublicense,
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and/or sell copies of the Software, and to permit persons to whom the
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Software is furnished to do so, subject to the following conditions:
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The above copyright notice and this permission notice (including the next
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paragraph) shall be included in all copies or substantial portions of the
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Software.
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THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
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SOFTWARE.
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-->
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<bifrost>
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<!-- Pseudo instruction representing dual texturing on Bifrost. Lowered to
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TEXC after register allocation, when the second destination register can
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be combined with the texture operation descriptor. -->
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<ins name="TEXC_DUAL" staging="rw=sr_count" pseudo="true" message="tex" dests="2" unit="add">
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<src start="0"/>
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<src start="3"/>
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<src start="6" mask="0xf7"/>
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<mod name="skip" start="9" size="1" opt="skip"/>
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<immediate name="sr_count" size="4" pseudo="true"/>
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<immediate name="sr_count_2" size="4" pseudo="true"/>
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<mod name="lod_mode" start="13" size="1" default="zero_lod" pseudo="true">
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<opt>computed_lod</opt>
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<opt>zero_lod</opt>
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</mod>
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</ins>
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<!--- Lowered to *SEG_ADD/+SEG_ADD -->
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<ins name="SEG_ADD.i64" pseudo="true" unit="add">
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<src start="0"/>
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<src start="3"/>
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<mod name="seg" size="3">
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<reserved/>
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<reserved/>
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<opt>wls</opt>
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<reserved/>
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<reserved/>
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<reserved/>
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<reserved/>
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<opt>tl</opt>
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</mod>
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<mod name="preserve_null" size="1" opt="preserve_null"/>
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</ins>
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<!-- Scheduler lowered to *ATOM_C.i32/+ATOM_CX. Real Valhall instructions. -->
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<ins name="ATOM_RETURN.i32" pseudo="true" staging="rw=sr_count" message="atomic" unit="add">
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<src start="0"/>
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<src start="3"/>
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<mod name="atom_opc" start="9" size="5">
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<reserved/>
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<reserved/>
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<opt>aadd</opt>
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<reserved/>
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<reserved/>
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<reserved/>
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<reserved/>
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<reserved/>
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<opt>asmin</opt>
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<opt>asmax</opt>
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<opt>aumin</opt>
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<opt>aumax</opt>
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<opt>aand</opt>
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<opt>aor</opt>
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<opt>axor</opt>
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<opt>axchg</opt> <!-- For Valhall -->
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<opt>acmpxchg</opt> <!-- For Valhall -->
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</mod>
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<!-- not actually encoded, but used for IR -->
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<immediate name="sr_count" size="4" pseudo="true"/>
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</ins>
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<ins name="ATOM1_RETURN.i32" pseudo="true" staging="w=sr_count" message="atomic" unit="add">
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<src start="0"/>
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<src start="3"/>
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<mod name="atom_opc" start="6" size="3">
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<opt>ainc</opt>
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<opt>adec</opt>
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<opt>aumax1</opt>
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<opt>asmax1</opt>
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<opt>aor1</opt>
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</mod>
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<!-- not actually encoded, but used for IR -->
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<immediate name="sr_count" size="4" pseudo="true"/>
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</ins>
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<ins name="ATOM.i32" pseudo="true" staging="r=sr_count" message="atomic" unit="add">
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<src start="0"/>
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<src start="3"/>
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<mod name="atom_opc" start="9" size="4">
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<reserved/>
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<reserved/>
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<opt>aadd</opt>
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<reserved/>
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<reserved/>
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<reserved/>
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<reserved/>
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<reserved/>
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<opt>asmin</opt>
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<opt>asmax</opt>
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<opt>aumin</opt>
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<opt>aumax</opt>
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<opt>aand</opt>
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<opt>aor</opt>
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<opt>axor</opt>
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</mod>
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<!-- not actually encoded, but used for IR -->
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<immediate name="sr_count" size="4" pseudo="true"/>
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</ins>
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<!-- *CUBEFACE1/+CUBEFACE2 pair, two destinations, scheduler lowered -->
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<ins name="CUBEFACE" pseudo="true" dests="2" unit="add">
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<src start="0"/>
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<src start="3"/>
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<src start="6"/>
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<mod name="neg0" size="1" opt="neg"/>
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<mod name="neg1" size="1" opt="neg"/>
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<mod name="neg2" size="1" opt="neg"/>
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</ins>
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<ins name="FABSNEG.f32" pseudo="true" unit="fma">
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<src start="0" mask="0xfb"/>
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<mod name="neg0" start="7" size="1" opt="neg"/>
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<mod name="abs0" start="12" size="1" opt="abs"/>
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<mod name="widen0" size="2">
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<opt>none</opt>
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<opt>h0</opt>
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<opt>h1</opt>
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</mod>
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</ins>
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<ins name="FABSNEG.v2f16" pseudo="true" unit="fma">
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<src start="0" mask="0xfb"/>
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<mod name="abs0" size="1" opt="abs"/>
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<mod name="neg0" start="7" size="1" opt="neg"/>
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<mod name="swz0" start="9" size="2" default="h01">
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<opt>h00</opt>
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<opt>h10</opt>
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<opt>h01</opt>
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<opt>h11</opt>
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</mod>
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</ins>
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<ins name="FCLAMP.f32" pseudo="true" unit="fma">
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<src start="0" mask="0xfb"/>
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<mod name="clamp" start="15" size="2">
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<opt>none</opt>
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<opt>clamp_0_inf</opt>
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<opt>clamp_m1_1</opt>
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<opt>clamp_0_1</opt>
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</mod>
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</ins>
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<ins name="FCLAMP.v2f16" pseudo="true" unit="fma">
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<src start="0" mask="0xfb"/>
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<mod name="clamp" start="15" size="2">
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<opt>none</opt>
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<opt>clamp_0_inf</opt>
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<opt>clamp_m1_1</opt>
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<opt>clamp_0_1</opt>
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</mod>
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</ins>
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<ins name="DISCARD.b32" pseudo="true" dests="0" unit="add">
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<src start="0"/>
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<mod name="widen0" size="2">
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<opt>none</opt>
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<opt>h0</opt>
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<opt>h1</opt>
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</mod>
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</ins>
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<ins name="PHI" pseudo="true" variable_srcs="true" unit="add"/>
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<ins name="COLLECT.i32" pseudo="true" variable_srcs="true" unit="add"/>
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<ins name="SPLIT.i32" pseudo="true" variable_dests="true" unit="add">
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<src start="0"/>
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</ins>
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</bifrost>
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