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canonicalize.py
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ac,radeonsi,winsyses: switch to SPDX-License-Identifier: MIT
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2023-05-24 21:48:19 +00:00 |
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gfx6.json
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radeonsi: follow shader_info.float_controls_execution_mode (mostly)
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2022-08-03 00:57:16 +00:00 |
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gfx7.json
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radeonsi: follow shader_info.float_controls_execution_mode (mostly)
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2022-08-03 00:57:16 +00:00 |
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gfx8.json
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radeonsi: follow shader_info.float_controls_execution_mode (mostly)
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2022-08-03 00:57:16 +00:00 |
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gfx9.json
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amd: update SX_BLEND_OPT_EPSILON.MRT0_EPSILON enum definitions
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2023-02-03 00:18:01 +00:00 |
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gfx10-rsrc.json
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amd/registers: update pitch definitions in descriptors
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2023-05-19 02:58:49 +00:00 |
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gfx10.json
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amd: update SX_BLEND_OPT_EPSILON.MRT0_EPSILON enum definitions
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2023-02-03 00:18:01 +00:00 |
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gfx11-rsrc.json
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amd/registers: update pitch definitions in descriptors
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2023-05-19 02:58:49 +00:00 |
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gfx11.json
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amd/registers: only define SPI and COMPUTE registers in the 0xB000 range
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2023-02-24 21:27:24 +00:00 |
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gfx81.json
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amd: update SX_BLEND_OPT_EPSILON.MRT0_EPSILON enum definitions
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2023-02-03 00:18:01 +00:00 |
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gfx103.json
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amd/registers: only define SPI and COMPUTE registers in the 0xB000 range
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2023-02-24 21:27:24 +00:00 |
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gfx940.json
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amd/registers: update gfx940.json
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2023-04-06 15:00:54 +00:00 |
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makeregheader.py
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ac,radeonsi,winsyses: switch to SPDX-License-Identifier: MIT
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2023-05-24 21:48:19 +00:00 |
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mergedbs.py
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ac,radeonsi,winsyses: switch to SPDX-License-Identifier: MIT
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2023-05-24 21:48:19 +00:00 |
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parse_kernel_headers.py
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amd/registers: fix the parser to include CP_COHER registers for gfx940
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2023-04-06 15:00:54 +00:00 |
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parseheader.py
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ac,radeonsi,winsyses: switch to SPDX-License-Identifier: MIT
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2023-05-24 21:48:19 +00:00 |
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pkt3.json
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amd/registers: use gfx9 packet definitions for gfx940
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2023-04-06 15:00:54 +00:00 |
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regdb.py
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ac,radeonsi,winsyses: switch to SPDX-License-Identifier: MIT
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2023-05-24 21:48:19 +00:00 |
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registers-manually-defined.json
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amd/registers: add gfx11.json
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2022-05-10 04:29:54 +00:00 |