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amd/registers: fix the parser to include CP_COHER registers for gfx940

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Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22158>
This commit is contained in:
Marek Olšák 2023-03-31 23:04:34 -04:00 • committed by Marge Bot
parent e917db3b42
commit e3bc800d5d
1 changed files with 9 additions and 6 deletions
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15
src/amd/registers/parse_kernel_headers.py
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@ -76,13 +76,14 @@ re_mask = re.compile(r'^#define (?P<name>\w+)__(?P<field>\w+)_MASK\s+(?P<value>[
def register_filter(gfx_level, name, offset, already_added):
group = offset // 0x1000
is_cdna = gfx_level in ['gfx940']
# Compute shader registers
umd_ranges = [0xB]
# Shader and uconfig registers
umd_ranges = [0xB, 0x30]
# Gfx context, uconfig, and perf counter registers
if gfx_level != 'gfx940':
umd_ranges += [0x28, 0x30, 0x31, 0x34, 0x35, 0x36, 0x37]
# Gfx context, other uconfig, and perf counter registers
if not is_cdna:
umd_ranges += [0x28, 0x31, 0x34, 0x35, 0x36, 0x37]
# Add all registers in the 0x8000 range for gfx6
if gfx_level == 'gfx6':
@ -109,7 +110,9 @@ def register_filter(gfx_level, name, offset, already_added):
not already_added and
'PREF_PRI_ACCUM' not in name and
# only define SPI and COMPUTE registers in the 0xB000 range.
(group != 0xB or name.startswith('SPI') or name.startswith('COMPUTE')))
(group != 0xB or name.startswith('SPI') or name.startswith('COMPUTE')) and
# only define CP_COHER uconfig registers on CDNA
(not is_cdna or group != 0x30 or name.startswith('CP_COHER')))
# Mapping from field names to enum types
enum_map = {