Vitaliy Triang3l Kuzmin a6ab0cff08 radv: Set DB_Z_INFO.NUM_SAMPLES to MSAA_EXPOSED_SAMPLES without Z/S ... This case is a new addition in GFX11, and according to PAL, when no depth/stencil attachment is bound, it must be set to the number of coverage samples (the number of SampleMask bits - which is MSAA_EXPOSED_SAMPLES): 4640888b57/src/core/hw/gfxip/gfx9/gfx9UniversalCmdBuffer.cpp (L6978) Without this change, the maximum of depth/stencil and color sample counts is used, and if there are no depth/stencil or color attachments (target- independent rasterization), the Depth Block assumes 1 coverage sample, and thus Primitive Ordered Pixel Shading doesn't work correctly (and fails 4xAA fragment shader interlock CTS tests), and occlusion queries don't count the correct number of samples (according to the "Sample Counting" section of the Vulkan specification, "the occlusion query sample counter increments by one for each sample with a coverage value of 1...") Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl> Signed-off-by: Vitaliy Triang3l Kuzmin <triang3l@yandex.ru> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22375>		2023-04-10 15:07:30 +00:00
..
addrlib	amd: update addrlib	2023-03-29 20:36:09 +00:00
ci	radv/ci: update expected failures with BONAIRE	2023-04-10 11:47:15 +00:00
common	ac/nir/ngg: fix store shared alignment	2023-04-07 03:42:25 +00:00
compiler	aco: don't use shared VGPRs for shaders consisting of multiple binaries	2023-04-04 18:35:43 +00:00
drm-shim	r300: use drm_shim_override	2022-11-16 14:37:47 +00:00
llvm	ac/llvm: Cover runtime 0 in GFX10 gs_alloc_req workaround.	2023-04-08 13:54:06 +00:00
registers	amd/registers: use gfx9 packet definitions for gfx940	2023-04-06 15:00:54 +00:00
vulkan	radv: Set DB_Z_INFO.NUM_SAMPLES to MSAA_EXPOSED_SAMPLES without Z/S	2023-04-10 15:07:30 +00:00
.clang-format	amd: Add radv_foreach_stage to ForEachMacros.	2023-03-27 08:29:35 +00:00
meson.build	meson: build radeon drm-shim also for r300 and r600	2022-11-16 14:37:47 +00:00