Samuel Pitoiset 74ab940156 radv: update binning settings to work around GPU hangs ... Ported from RadeonSI, but it seems PAL always use 1 for both parameters as well. This should fix random GPU hangs with small chips (eg. NAVI24, GFX1103), though all chips might have been affected. Cc: mesa-stable Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/8046 Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/8597 Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/8683 Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22528>		2023-04-20 18:12:52 +00:00
..
addrlib	amd: update addrlib	2023-03-29 20:36:09 +00:00
ci	radv: do not allow 1D block-compressed images with (extended) storage on GFX6	2023-04-20 08:20:50 +00:00
common	nir: add next_stage parameter to nir_remove_varying	2023-04-19 21:42:11 +00:00
compiler	aco: fix nir_f2u64 translation	2023-04-20 06:32:15 +00:00
drm-shim	amd: fix typos	2023-04-13 23:08:22 +00:00
llvm	ac/llvm,radeonsi: lower nir_load_point_coord_maybe_flipped in nir	2023-04-19 01:59:02 +00:00
registers	amd/registers: use gfx9 packet definitions for gfx940	2023-04-06 15:00:54 +00:00
vulkan	radv: update binning settings to work around GPU hangs	2023-04-20 18:12:52 +00:00
.clang-format	amd: Add radv_foreach_stage to ForEachMacros.	2023-03-27 08:29:35 +00:00
meson.build	meson: build radeon drm-shim also for r300 and r600	2022-11-16 14:37:47 +00:00