Commit graph

11965 commits

Author SHA1 Message Date
Samuel Pitoiset
74ab940156 radv: update binning settings to work around GPU hangs
Ported from RadeonSI, but it seems PAL always use 1 for both
parameters as well.

This should fix random GPU hangs with small chips (eg. NAVI24, GFX1103),
though all chips might have been affected.

Cc: mesa-stable
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/8046
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/8597
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/8683
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22528>
2023-04-20 18:12:52 +00:00
André Almeida
d99211b22c radv: debug: Update decode ring umr command
The old ring decoder command is deprecated since umr release 1.0.4 and
was effectively removed at 1.0.7. Update the command to use the new
decode flag.

Signed-off-by: André Almeida <andrealmeid@igalia.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Tatsuyuki Ishi <ishitatsuyuki@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22576>
2023-04-20 17:26:43 +00:00
Samuel Pitoiset
6bc2dce228 radv: use gfx_level in radv_flush_occlusion_query_state()
Cleanup.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22556>
2023-04-20 16:25:09 +00:00
Samuel Pitoiset
fbab8df43f radv: emit PIXEL_PIPE_STAT_CONTROL in the gfx preamble for GFX11
This is more optimal than emitting for every BeginOcclusionQuery().

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22556>
2023-04-20 16:25:09 +00:00
Samuel Pitoiset
c1d32880f7 radv: track DB_COUNT_CONTROL changes to avoid context rolls
This can be really noticeable for the BeginQuery/Draw/EndQuery pattern.
It seems to improve a depth-only pass by +35% in one upcoming game
because this removes a bunch of context rolls.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22556>
2023-04-20 16:25:09 +00:00
Samuel Pitoiset
02443d752e radv: delay enabling/disabling occlusion queries at draw time
Most applications have a sequence like BeginQuery/Draw/EndQuery which
can be optimized by delaying DB_COUNT_CONTROL at draw time instead of
enabling/disabling for every draw.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22556>
2023-04-20 16:25:09 +00:00
Samuel Pitoiset
d44651bfc3 radv: wait for occlusion queries in the resolve query shader
This is really noticeable for games that resolve a bunch of occlusion
queries (in this case 4096) because it seems that emitting 4096
WAIT_REG_MEM packets can stall more than expected. Fixes this by
waiting for queries in the resolve query shader.

This improves performance of an unreleased game by +~10% (71->78 FPS).
RADV should now be really close to Windows performance for that title.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22579>
2023-04-20 14:11:26 +00:00
Samuel Pitoiset
72a522fb36 radv: fix usage flag for 3D compressed 128 bpp images on GFX9
VK_FORMAT_FEATURE_2_COLOR_ATTACHMENT_BIT is equal to
VK_IMAGE_USAGE_INPUT_ATTACHMENT_BIT but we want COLOR_ATTACHMENT_BIT.

Found by inspection.

Cc: mesa-stable
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22540>
2023-04-20 08:20:50 +00:00
Samuel Pitoiset
8a2fab66de radv: do not allow 1D block-compressed images with (extended) storage on GFX6
For some reasons this seems broken only on GFX6. Note that PAL doesn't
allowed block-compressed with 1D on all GPUs.

Cc: mesa-stable
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22540>
2023-04-20 08:20:50 +00:00
Qiang Yu
6a39d35df0 aco: fix nir_f2u64 translation
mantissa needs to be at the lower part for shift left.
This fixes large integer value conversion.

Cc: mesa-stable
Reviewed-by: Georg Lehmann <dadschoorse@gmail.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22570>
2023-04-20 06:32:15 +00:00
Emma Anholt
392266ad6a ci/radv: Add known flakes for #8817
Should greatly increase Marge reliability.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22562>
2023-04-20 02:22:41 +00:00
Emma Anholt
2a9b990fa3 ci/radv: Demote navi21 to manual until recent flakiness resolves.
22 detected job flakes yesterday.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22562>
2023-04-20 02:22:40 +00:00
Timur Kristóf
b32556b058 radv: Fix dword alignment in SDMA buffer copy.
Also add a comment that explains the dword aligned mode.

Note that the SDMA shader uploads are always dword aligned
so this commit doesn't fix any issues but just prepares this
function for more general use.

Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Tatsuyuki Ishi <ishitatsuyuki@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22551>
2023-04-20 00:46:01 +00:00
Marek Olšák
e6e406b483 nir: add next_stage parameter to nir_remove_varying
so that e.g. the POS output is removed if the next stage is not FS.

Reviewed-by: Qiang Yu <yuq825@gmail.com>
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21861>
2023-04-19 21:42:11 +00:00
Rhys Perry
5db64fcc8c aco: use apply_nuw_to_ssa() with load_smem_amd
fossil-db (navi21):
Totals from 107 (0.08% of 135636) affected shaders:
Instrs: 389667 -> 389425 (-0.06%); split: -0.06%, +0.00%
CodeSize: 2050380 -> 2049440 (-0.05%); split: -0.05%, +0.00%
Latency: 3738053 -> 3737313 (-0.02%); split: -0.02%, +0.00%
InvThroughput: 599889 -> 599790 (-0.02%); split: -0.02%, +0.00%
SClause: 16120 -> 15920 (-1.24%)
Copies: 29823 -> 29809 (-0.05%); split: -0.07%, +0.02%
PreSGPRs: 6856 -> 6849 (-0.10%)

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Qiang Yu <yuq825@gmail.com>
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22553>
2023-04-19 19:29:48 +00:00
Rhys Perry
1a6095b36e aco: remove SMEM_instruction::prevent_overflow
This doesn't seem useful anymore, and it seems we forgot to set it in a
few places.

This commit changes the behaviour of the optimizer so that
prevent_overflow is always true.

fossil-db (navi21):
Totals from 7421 (5.47% of 135636) affected shaders:
Instrs: 5402823 -> 5440126 (+0.69%); split: -0.00%, +0.69%
CodeSize: 28731300 -> 28974152 (+0.85%); split: -0.00%, +0.85%
VGPRs: 317528 -> 317552 (+0.01%)
SpillSGPRs: 419 -> 415 (-0.95%)
Latency: 40712478 -> 40783115 (+0.17%); split: -0.01%, +0.19%
InvThroughput: 7612708 -> 7616751 (+0.05%); split: -0.00%, +0.06%
VClause: 123824 -> 123848 (+0.02%); split: -0.09%, +0.11%
SClause: 161915 -> 172741 (+6.69%); split: -0.03%, +6.71%
Copies: 393015 -> 394429 (+0.36%); split: -0.20%, +0.56%
PreSGPRs: 288658 -> 289603 (+0.33%); split: -0.04%, +0.36%

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Qiang Yu <yuq825@gmail.com>
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/8864
Cc: mesa-stable
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22553>
2023-04-19 19:29:48 +00:00
Daniel Schürmann
b288ec803c radv/rt: fix total stack size computation
Fixes: 2649a1f272 ('radv/rt: introduce and set rt_pipeline->stack_size ')
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22526>
2023-04-19 12:26:53 +00:00
Timur Kristóf
acce5c3fe1 radv: Enable IB2 workaround on all indirect draws.
IB2 packets hang GFX6 when they contain any indirect draws,
not just the MULTI versions.

Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Tatsuyuki Ishi <ishitatsuyuki@gmail.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22533>
2023-04-19 09:27:52 +00:00
Timur Kristóf
46a14390d8 radv: Remove IB2 workaround from mesh shader draws.
The GPUs which need the workaround do not support mesh shaders.

Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Tatsuyuki Ishi <ishitatsuyuki@gmail.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22533>
2023-04-19 09:27:52 +00:00
Timur Kristóf
d16d9ef345 radv: Simplify IB2 workaround.
Move compute IB2 check to the winsys, because IB2 only works on
GFX queues and not any other queue types.

Then, simplify the workaround condition in the cmd buffer.

Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Tatsuyuki Ishi <ishitatsuyuki@gmail.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22533>
2023-04-19 09:27:52 +00:00
Qiang Yu
fbe7aec446 aco: skip scratch buffer init when its arg is not used
radeonsi does not pass scratch buffer address by arg,
but dynamical relocation symbol when upload. Just skip
this part to enable radeonsi use aco, but it will fail
when spill.

Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22525>
2023-04-19 08:39:46 +00:00
Qiang Yu
9cd3aa173a aco: implement nir_bindless_image_atomic_inc/dec_wrap
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22525>
2023-04-19 08:39:46 +00:00
Qiang Yu
31bfad83ec aco: support 32bit address in nir_load_smem_amd
radeonsi uses 32bit address.

Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22525>
2023-04-19 08:39:46 +00:00
Qiang Yu
3ff9153a3b ac,radv: move ps arg compation to common place
To be shared with radeonsi when aco is used.

Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22525>
2023-04-19 08:39:46 +00:00
Tatsuyuki Ishi
3678c28d3d util: Call mesa_bytes_to_hex directly instead of disk_cache_format_hex_id.
The formatting is nothing specific about the disk cache.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22527>
2023-04-19 04:19:51 +00:00
Qiang Yu
feeae0f18f ac/llvm,radeonsi: lower nir_load_point_coord_maybe_flipped in nir
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22523>
2023-04-19 01:59:02 +00:00
Qiang Yu
f7f0d31fcc nir,ac/llvm,radeonsi: replace nir_load_smem_buffer_amd with nir_load_ubo
They use same instruction. Just because when the time
nir_load_smem_buffer_amd was introduced, radeonsi didn't support
pass buffer descriptor to nir_load_ubo directly.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22523>
2023-04-19 01:59:02 +00:00
Qiang Yu
75b75c6c0a ac/llvm,radeonsi: use texture non-uniform flag as waterfall switch
Also for calling nir_lower_non_uniform_access() when ACO.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22523>
2023-04-19 01:59:02 +00:00
Eric Engestrom
0a0e485421 amd: fix buggy usage of unreachable()
Cc: mesa-stable
Signed-off-by: Eric Engestrom <eric@igalia.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22529>
2023-04-18 13:59:54 +00:00
Rhys Perry
d291f368a0 ac/llvm: support implicit LOD for nir_texop_tg4
Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Georg Lehmann <dadschoorse@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22315>
2023-04-18 10:42:07 +00:00
Rhys Perry
25b1974e1b aco: support implicit LOD for nir_texop_tg4
Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Georg Lehmann <dadschoorse@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22315>
2023-04-18 10:42:07 +00:00
Samuel Pitoiset
c221bfbd85 radv/amdgpu: remove legacy code for querying context status
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22521>
2023-04-18 06:55:03 +00:00
Samuel Pitoiset
767a9324b9 radv/amdgpu: remove legacy code path for creating the BO list
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22521>
2023-04-18 06:55:03 +00:00
Samuel Pitoiset
c920d676c0 radv: require DRM 3.27
Linux kernel 4.20+ is now required to use RADV.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22521>
2023-04-18 06:55:03 +00:00
Samuel Pitoiset
0d7912d239 radv: disable fast-clears with CMASK for 128-bit formats
This isn't supported according to RadeonSI.

This fixes a piglit test with Zink that uses a R32G32B32A32_SINT format
with MSAA 8x. This is because DCC fast-clears with MSAA require to
clear CMASK too.

Cc: mesa-stable
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/7313
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22462>
2023-04-17 06:19:34 +00:00
Qiang Yu
cc891e871e ac/llvm,radeonsi: lower ps color load in nir
Remove the color0/1 in ac_shader_abi which is used by
radeonsi only.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21683>
2023-04-17 02:11:56 +00:00
Qiang Yu
35d5c7c251 ac/nir/ps: lower sample mask input when needed
Ported from si_llvm_build_ps_prolog().

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21683>
2023-04-17 02:11:56 +00:00
Qiang Yu
1103d4ed74 ac/nir/ps: add force lower barycentric load options
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21683>
2023-04-17 02:11:55 +00:00
Qiang Yu
0e4ac0c1d6 ac/nir/ps: lower barycentric load when bc_optimize
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21683>
2023-04-17 02:11:55 +00:00
David Heidelberg
c690644842 ci/amd: update checksums after DXVK 2.1 update
Heaven got fixed with DXVK 2.1.

Signed-off-by: David Heidelberg <david.heidelberg@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22447>
2023-04-15 10:57:06 +00:00
David Heidelberg
0dcb3994a5 ci/amd: 4/5 runners TPad-C13 runners are online, restore most of the tests
Partial revert of 590959057c ("ci/amd: raven is currently downgraded
to 2 machines only, adapt")

Test which remains disabled: radeonsi-raven-va:amd64 (VAAPI testing).

Signed-off-by: David Heidelberg <david.heidelberg@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22447>
2023-04-15 10:57:06 +00:00
Samuel Pitoiset
3ad751f043 radv: tidy up dirtying RBPLUS state in radv_bind_dynamic_state()
To dirty driver specific states at the same place.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22472>
2023-04-14 17:49:23 +00:00
Samuel Pitoiset
ba71b142f8 radv: re-emit the guardband state when related PSO are bound
If one of the related states is static, the guardband state needs to be
re-emitted when a graphics pipeline is bound.

Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/8828
Fixes: 40d8df7280 ("radv: emit the guardband state separately from the scissor state")
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22472>
2023-04-14 17:49:23 +00:00
Samuel Pitoiset
f11a4a09b0 radv: try to keep HTILE compressed for READ_ONLY_OPTIMAL layout
It should be handled like DEPTH_STENCIL_READ_ONLY_OPTIMAL.

This fixes an issue with VRS attachment because HTILE was considered
disabled for READ_ONLY_OPTIMAL but there is no reasons to disable it
as long as the image is only used as a depth/stencil attachment.

Otherwise, when HTILE is disabled, VRS rates are ignored.

Cc: mesa-stable
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/8675
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22468>
2023-04-14 13:48:04 +00:00
Timur Kristóf
948a122f30 amd: Rename INDIRECT_BUFFER_CIK to just INDIRECT_BUFFER.
This packet is supported on GFX6 too, its name should relect that.

Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22406>
2023-04-13 23:58:48 +00:00
Timur Kristóf
7ddac41f3f radv: Chain command buffers on GFX6 in radv_queue.
Also don't check whether chaining is enabled in radv_queue, the
winsys will take care of that anyway.

Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22406>
2023-04-13 23:58:48 +00:00
Timur Kristóf
d6518fd357 radv: Use IB BOs (chaining) by default on GFX6.
GFX6 supports IB chaining since the PFP firmware version 20.
Note that the very first amdgpu firmware for GFX6 already had
version 29, so we can assume that all GPUs supported by RADV
have this feature.

Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22406>
2023-04-13 23:58:47 +00:00
Timur Kristóf
0e7244ce18 radv: Disallow IB2 on GFX6 when using draw_indirect_multi.
GFX6 has the same problem as GFX7 here.

Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22406>
2023-04-13 23:58:47 +00:00
Timur Kristóf
add3b34c17 radv/amdgpu: Remove unnecessary assertions from chaining.
These used to guard against chaining on GFX6 and on HW IP types
that don't support chaining, but these things are now guarded
elsewhere and these assertions are no longer necessary.

Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22406>
2023-04-13 23:58:47 +00:00
Harri Nieminen
f85f511a38 amd: fix typos in code
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22432>
2023-04-13 23:08:22 +00:00