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9cbc3ab239
For the non-ssa case, we were trying to use reg->num_components. But this is not the same that nir_ssa_def_components_read. It is the number of components of the destination register. And in the 16bit case, even if nir_lower_tex packs the outcome, it doesn't update the number of components, as nir_tex_instr_dest_size would still return 4. And nir validate would check that those values are the same. So this change focuses on the last part of this comment at nir_lower_tex: * Note that we don't change the destination num_components, because * nir_tex_instr_dest_size() will still return 4. The driver is just * expected to not store the other channels, given that nothing at the * NIR level will read them. We just limit how many channels we would use for the f16 case. It is also worth to note, based on the CTS and different applications we test, that this is a corner case. This was detected when we experimented to enable nir_opt_gcm for v3d, that lead to raise an assertion slightly below with some shaderdb tests, but technically it could happen without it. Reviewed-by: Iago Toral Quiroga <itoral@igalia.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17185> |
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| .. | ||
| meson.build | ||
| nir_to_vir.c | ||
| qpu_schedule.c | ||
| qpu_validate.c | ||
| v3d33_tex.c | ||
| v3d33_vpm_setup.c | ||
| v3d40_tex.c | ||
| v3d_compiler.h | ||
| v3d_nir_lower_image_load_store.c | ||
| v3d_nir_lower_io.c | ||
| v3d_nir_lower_line_smooth.c | ||
| v3d_nir_lower_load_store_bitsize.c | ||
| v3d_nir_lower_logic_ops.c | ||
| v3d_nir_lower_robust_access.c | ||
| v3d_nir_lower_scratch.c | ||
| v3d_nir_lower_txf_ms.c | ||
| vir.c | ||
| vir_dump.c | ||
| vir_live_variables.c | ||
| vir_opt_constant_alu.c | ||
| vir_opt_copy_propagate.c | ||
| vir_opt_dead_code.c | ||
| vir_opt_redundant_flags.c | ||
| vir_opt_small_immediates.c | ||
| vir_register_allocate.c | ||
| vir_to_qpu.c | ||