Danylo Piliaiev 99457286c9 ir3/a7xx: Add ccinv instruction ... _Presumably_ invalidates workgroup-wide cache for image/buffer data access. so while "fence" is enough to synchronize data access inside a workgroup, for cross-workgroup synchronization we have to invalidate that cache. Signed-off-by: Danylo Piliaiev <dpiliaiev@igalia.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23217>		2023-09-05 16:19:30 +00:00
..
encode.c	ir3, isaspec: add raw instruction to assembler/disassembler.	2023-01-26 14:26:11 +00:00
ir3-cat0.xml	ir3: Parse (eq) flag	2023-08-10 10:09:27 +00:00
ir3-cat1.xml	ir3/a7xx: Add definitions for (last) src GPR attribute	2023-04-27 21:06:47 +00:00
ir3-cat2.xml	ir3: Add support for (dis)assembling flat.b	2021-11-04 02:59:28 +00:00
ir3-cat3.xml	ir3/a7xx: Add definitions for (last) src GPR attribute	2023-04-27 21:06:47 +00:00
ir3-cat4.xml	freedreno/isa: Convert to srcs/dsts	2021-06-23 17:20:29 +00:00
ir3-cat5.xml	ir3/a7xx: cat5 mode1 has swapped tex/samp ids	2023-09-05 16:19:29 +00:00
ir3-cat6.xml	ir3/a7xx: Don't multiply global mem instruction's offset by 4	2023-09-05 16:19:29 +00:00
ir3-cat7.xml	ir3/a7xx: Add ccinv instruction	2023-09-05 16:19:30 +00:00
ir3-common.xml	ir3/a7xx: Add definitions for (last) src GPR attribute	2023-04-27 21:06:47 +00:00
ir3-disasm.c	isaspec: Rename isa_decode() to isa_disasm()	2023-07-28 18:41:58 +00:00
ir3.xml	freedreno/isa: Convert to srcs/dsts	2021-06-23 17:20:29 +00:00
isa.h	isaspec: Move isa_decode(..) declaration	2022-09-03 19:26:04 +00:00
meson.build	freedreno: decouple compiler and vulkan driver from gallium	2023-08-03 07:29:36 +00:00