mesa/src/freedreno/ir3
Jason Ekstrand 80e8dfe9de nir: Rename Boolean-related opcodes to include 32 in the name
This is a squash of a bunch of individual changes:

    nir/builder: Generate 32-bit bool opcodes transparently

    nir/algebraic: Remap Boolean opcodes to the 32-bit variant

    Use 32-bit opcodes in the NIR producers and optimizations

        Generated with a little hand-editing and the following sed commands:

        sed -i 's/nir_op_ball_fequal/nir_op_b32all_fequal/g' **/*.c
        sed -i 's/nir_op_bany_fnequal/nir_op_b32any_fnequal/g' **/*.c
        sed -i 's/nir_op_ball_iequal/nir_op_b32all_iequal/g' **/*.c
        sed -i 's/nir_op_bany_inequal/nir_op_b32any_inequal/g' **/*.c
        sed -i 's/nir_op_\([fiu]lt\)/nir_op_\132/g' **/*.c
        sed -i 's/nir_op_\([fiu]ge\)/nir_op_\132/g' **/*.c
        sed -i 's/nir_op_\([fiu]ne\)/nir_op_\132/g' **/*.c
        sed -i 's/nir_op_\([fiu]eq\)/nir_op_\132/g' **/*.c
        sed -i 's/nir_op_\([fi]\)ne32g/nir_op_\1neg/g' **/*.c
        sed -i 's/nir_op_bcsel/nir_op_b32csel/g' **/*.c

     Use 32-bit opcodes in the NIR back-ends

        Generated with a little hand-editing and the following sed commands:

        sed -i 's/nir_op_ball_fequal/nir_op_b32all_fequal/g' **/*.c
        sed -i 's/nir_op_bany_fnequal/nir_op_b32any_fnequal/g' **/*.c
        sed -i 's/nir_op_ball_iequal/nir_op_b32all_iequal/g' **/*.c
        sed -i 's/nir_op_bany_inequal/nir_op_b32any_inequal/g' **/*.c
        sed -i 's/nir_op_\([fiu]lt\)/nir_op_\132/g' **/*.c
        sed -i 's/nir_op_\([fiu]ge\)/nir_op_\132/g' **/*.c
        sed -i 's/nir_op_\([fiu]ne\)/nir_op_\132/g' **/*.c
        sed -i 's/nir_op_\([fiu]eq\)/nir_op_\132/g' **/*.c
        sed -i 's/nir_op_\([fi]\)ne32g/nir_op_\1neg/g' **/*.c
        sed -i 's/nir_op_bcsel/nir_op_b32csel/g' **/*.c

Reviewed-by: Eric Anholt <eric@anholt.net>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Tested-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
2018-12-16 21:03:02 +00:00
..
disasm-a3xx.c freedreno/ir3: sync instr/disasm 2018-12-07 13:49:21 -05:00
instr-a3xx.h freedreno/ir3: sync instr/disasm 2018-12-07 13:49:21 -05:00
ir3.c freedreno: move ir3 to common location 2018-11-27 15:44:02 -05:00
ir3.h freedreno/ir3: code-motion 2018-12-07 13:49:21 -05:00
ir3_compiler.c freedreno: move ir3 to common location 2018-11-27 15:44:02 -05:00
ir3_compiler.h freedreno: move ir3 to common location 2018-11-27 15:44:02 -05:00
ir3_compiler_nir.c nir: Rename Boolean-related opcodes to include 32 in the name 2018-12-16 21:03:02 +00:00
ir3_context.c freedreno/ir3: code-motion 2018-12-07 13:49:21 -05:00
ir3_context.h freedreno/ir3: track max flow control depth for a5xx/a6xx 2018-12-07 13:49:21 -05:00
ir3_cp.c freedreno: move ir3 to common location 2018-11-27 15:44:02 -05:00
ir3_depth.c freedreno/ir3: don't remove unused input components 2018-12-13 15:51:01 -05:00
ir3_group.c freedreno: move ir3 to common location 2018-11-27 15:44:02 -05:00
ir3_legalize.c freedreno: move ir3 to common location 2018-11-27 15:44:02 -05:00
ir3_nir.c freedreno: move ir3 to common location 2018-11-27 15:44:02 -05:00
ir3_nir.h freedreno: move ir3 to common location 2018-11-27 15:44:02 -05:00
ir3_nir_lower_tg4_to_tex.c freedreno: move ir3 to common location 2018-11-27 15:44:02 -05:00
ir3_nir_trig.py freedreno: move ir3 to common location 2018-11-27 15:44:02 -05:00
ir3_print.c freedreno: move ir3 to common location 2018-11-27 15:44:02 -05:00
ir3_ra.c freedreno/ir3: don't fetch unused tex components 2018-12-07 13:49:21 -05:00
ir3_sched.c freedreno: move ir3 to common location 2018-11-27 15:44:02 -05:00
ir3_shader.c freedreno: debug GEM obj names 2018-12-13 15:51:01 -05:00
ir3_shader.h freedreno/ir3: track max flow control depth for a5xx/a6xx 2018-12-07 13:49:21 -05:00
meson.build freedreno/ir3: code-motion 2018-12-07 13:49:21 -05:00