mirror of
https://gitlab.freedesktop.org/mesa/mesa.git
synced 2026-01-07 02:10:12 +01:00
freedreno/ir3: code-motion
Split up ir3_compiler_nir.c a bit before starting to add new stuff for a6xx SSBO/image instructions. Signed-off-by: Rob Clark <robdclark@gmail.com>
This commit is contained in:
Rob Clark
parent
e37351fa57
commit
9517037bdc
6 changed files with 942 additions and 838 deletions
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@ -22,6 +22,8 @@ ir3_SOURCES := \
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ir3/ir3_compiler.c \
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ir3/ir3_compiler.h \
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ir3/ir3_compiler_nir.c \
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ir3/ir3_context.c \
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ir3/ir3_context.h \
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ir3/ir3_cp.c \
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ir3/ir3_depth.c \
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ir3/ir3_group.c \
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@ -1012,6 +1012,59 @@ void ir3_legalize(struct ir3 *ir, int *num_samp, bool *has_ssbo, int *max_bary);
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/* ************************************************************************* */
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/* instruction helpers */
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static inline struct ir3_instruction *
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create_immed_typed(struct ir3_block *block, uint32_t val, type_t type)
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{
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struct ir3_instruction *mov;
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unsigned flags = (type_size(type) < 32) ? IR3_REG_HALF : 0;
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mov = ir3_instr_create(block, OPC_MOV);
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mov->cat1.src_type = type;
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mov->cat1.dst_type = type;
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ir3_reg_create(mov, 0, flags);
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ir3_reg_create(mov, 0, IR3_REG_IMMED)->uim_val = val;
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return mov;
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}
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static inline struct ir3_instruction *
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create_immed(struct ir3_block *block, uint32_t val)
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{
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return create_immed_typed(block, val, TYPE_U32);
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}
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static inline struct ir3_instruction *
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create_uniform(struct ir3_block *block, unsigned n)
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{
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struct ir3_instruction *mov;
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mov = ir3_instr_create(block, OPC_MOV);
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/* TODO get types right? */
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mov->cat1.src_type = TYPE_F32;
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mov->cat1.dst_type = TYPE_F32;
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ir3_reg_create(mov, 0, 0);
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ir3_reg_create(mov, n, IR3_REG_CONST);
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return mov;
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}
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static inline struct ir3_instruction *
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create_uniform_indirect(struct ir3_block *block, int n,
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struct ir3_instruction *address)
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{
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struct ir3_instruction *mov;
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mov = ir3_instr_create(block, OPC_MOV);
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mov->cat1.src_type = TYPE_U32;
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mov->cat1.dst_type = TYPE_U32;
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ir3_reg_create(mov, 0, 0);
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ir3_reg_create(mov, 0, IR3_REG_CONST | IR3_REG_RELATIV)->array.offset = n;
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ir3_instr_set_address(mov, address);
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return mov;
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}
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/* creates SSA src of correct type (ie. half vs full precision) */
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static inline struct ir3_register * __ssa_src(struct ir3_instruction *instr,
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struct ir3_instruction *src, unsigned flags)
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File diff suppressed because it is too large
Load diff
593
src/freedreno/ir3/ir3_context.c
Normal file
593
src/freedreno/ir3/ir3_context.c
Normal file
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@ -0,0 +1,593 @@
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/*
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* Copyright (C) 2015-2018 Rob Clark <robclark@freedesktop.org>
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice (including the next
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* paragraph) shall be included in all copies or substantial portions of the
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* Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
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* SOFTWARE.
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*
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* Authors:
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* Rob Clark <robclark@freedesktop.org>
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*/
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#include "util/u_math.h"
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#include "ir3_compiler.h"
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#include "ir3_context.h"
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#include "ir3_shader.h"
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#include "ir3_nir.h"
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struct ir3_context *
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ir3_context_init(struct ir3_compiler *compiler,
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struct ir3_shader_variant *so)
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{
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struct ir3_context *ctx = rzalloc(NULL, struct ir3_context);
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if (compiler->gpu_id >= 400) {
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if (so->type == MESA_SHADER_VERTEX) {
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ctx->astc_srgb = so->key.vastc_srgb;
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} else if (so->type == MESA_SHADER_FRAGMENT) {
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ctx->astc_srgb = so->key.fastc_srgb;
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}
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} else {
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if (so->type == MESA_SHADER_VERTEX) {
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ctx->samples = so->key.vsamples;
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} else if (so->type == MESA_SHADER_FRAGMENT) {
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ctx->samples = so->key.fsamples;
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}
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}
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ctx->compiler = compiler;
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ctx->so = so;
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ctx->def_ht = _mesa_hash_table_create(ctx,
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_mesa_hash_pointer, _mesa_key_pointer_equal);
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ctx->block_ht = _mesa_hash_table_create(ctx,
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_mesa_hash_pointer, _mesa_key_pointer_equal);
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/* TODO: maybe generate some sort of bitmask of what key
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* lowers vs what shader has (ie. no need to lower
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* texture clamp lowering if no texture sample instrs)..
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* although should be done further up the stack to avoid
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* creating duplicate variants..
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*/
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if (ir3_key_lowers_nir(&so->key)) {
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nir_shader *s = nir_shader_clone(ctx, so->shader->nir);
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ctx->s = ir3_optimize_nir(so->shader, s, &so->key);
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} else {
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/* fast-path for shader key that lowers nothing in NIR: */
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ctx->s = so->shader->nir;
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}
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/* this needs to be the last pass run, so do this here instead of
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* in ir3_optimize_nir():
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*/
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NIR_PASS_V(ctx->s, nir_lower_locals_to_regs);
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NIR_PASS_V(ctx->s, nir_convert_from_ssa, true);
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if (ir3_shader_debug & IR3_DBG_DISASM) {
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DBG("dump nir%dv%d: type=%d, k={cts=%u,hp=%u}",
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so->shader->id, so->id, so->type,
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so->key.color_two_side, so->key.half_precision);
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nir_print_shader(ctx->s, stdout);
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}
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if (shader_debug_enabled(so->type)) {
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fprintf(stderr, "NIR (final form) for %s shader:\n",
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_mesa_shader_stage_to_string(so->type));
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nir_print_shader(ctx->s, stderr);
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}
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ir3_nir_scan_driver_consts(ctx->s, &so->const_layout);
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so->num_uniforms = ctx->s->num_uniforms;
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so->num_ubos = ctx->s->info.num_ubos;
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/* Layout of constant registers, each section aligned to vec4. Note
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* that pointer size (ubo, etc) changes depending on generation.
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*
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* user consts
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* UBO addresses
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* SSBO sizes
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* if (vertex shader) {
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* driver params (IR3_DP_*)
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* if (stream_output.num_outputs > 0)
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* stream-out addresses
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* }
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* immediates
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*
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* Immediates go last mostly because they are inserted in the CP pass
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* after the nir -> ir3 frontend.
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*/
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unsigned constoff = align(ctx->s->num_uniforms, 4);
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unsigned ptrsz = ir3_pointer_size(ctx);
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memset(&so->constbase, ~0, sizeof(so->constbase));
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if (so->num_ubos > 0) {
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so->constbase.ubo = constoff;
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constoff += align(ctx->s->info.num_ubos * ptrsz, 4) / 4;
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}
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if (so->const_layout.ssbo_size.count > 0) {
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unsigned cnt = so->const_layout.ssbo_size.count;
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so->constbase.ssbo_sizes = constoff;
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constoff += align(cnt, 4) / 4;
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}
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if (so->const_layout.image_dims.count > 0) {
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unsigned cnt = so->const_layout.image_dims.count;
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so->constbase.image_dims = constoff;
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constoff += align(cnt, 4) / 4;
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}
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unsigned num_driver_params = 0;
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if (so->type == MESA_SHADER_VERTEX) {
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num_driver_params = IR3_DP_VS_COUNT;
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} else if (so->type == MESA_SHADER_COMPUTE) {
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num_driver_params = IR3_DP_CS_COUNT;
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}
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so->constbase.driver_param = constoff;
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constoff += align(num_driver_params, 4) / 4;
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if ((so->type == MESA_SHADER_VERTEX) &&
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(compiler->gpu_id < 500) &&
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so->shader->stream_output.num_outputs > 0) {
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so->constbase.tfbo = constoff;
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constoff += align(IR3_MAX_SO_BUFFERS * ptrsz, 4) / 4;
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}
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so->constbase.immediate = constoff;
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return ctx;
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}
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void
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ir3_context_free(struct ir3_context *ctx)
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{
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ralloc_free(ctx);
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}
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/*
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* Misc helpers
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*/
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/* allocate a n element value array (to be populated by caller) and
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* insert in def_ht
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*/
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struct ir3_instruction **
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ir3_get_dst_ssa(struct ir3_context *ctx, nir_ssa_def *dst, unsigned n)
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{
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struct ir3_instruction **value =
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ralloc_array(ctx->def_ht, struct ir3_instruction *, n);
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_mesa_hash_table_insert(ctx->def_ht, dst, value);
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return value;
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}
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struct ir3_instruction **
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ir3_get_dst(struct ir3_context *ctx, nir_dest *dst, unsigned n)
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{
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struct ir3_instruction **value;
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if (dst->is_ssa) {
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value = ir3_get_dst_ssa(ctx, &dst->ssa, n);
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} else {
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value = ralloc_array(ctx, struct ir3_instruction *, n);
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}
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/* NOTE: in non-ssa case, we don't really need to store last_dst
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* but this helps us catch cases where put_dst() call is forgotten
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*/
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compile_assert(ctx, !ctx->last_dst);
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ctx->last_dst = value;
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ctx->last_dst_n = n;
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return value;
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}
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struct ir3_instruction * const *
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ir3_get_src(struct ir3_context *ctx, nir_src *src)
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{
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if (src->is_ssa) {
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struct hash_entry *entry;
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entry = _mesa_hash_table_search(ctx->def_ht, src->ssa);
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compile_assert(ctx, entry);
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return entry->data;
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} else {
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nir_register *reg = src->reg.reg;
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struct ir3_array *arr = ir3_get_array(ctx, reg);
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unsigned num_components = arr->r->num_components;
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struct ir3_instruction *addr = NULL;
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struct ir3_instruction **value =
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ralloc_array(ctx, struct ir3_instruction *, num_components);
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if (src->reg.indirect)
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addr = ir3_get_addr(ctx, ir3_get_src(ctx, src->reg.indirect)[0],
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reg->num_components);
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for (unsigned i = 0; i < num_components; i++) {
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unsigned n = src->reg.base_offset * reg->num_components + i;
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compile_assert(ctx, n < arr->length);
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value[i] = ir3_create_array_load(ctx, arr, n, addr);
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}
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return value;
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}
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}
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void
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put_dst(struct ir3_context *ctx, nir_dest *dst)
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{
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unsigned bit_size = nir_dest_bit_size(*dst);
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if (bit_size < 32) {
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for (unsigned i = 0; i < ctx->last_dst_n; i++) {
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struct ir3_instruction *dst = ctx->last_dst[i];
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dst->regs[0]->flags |= IR3_REG_HALF;
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if (ctx->last_dst[i]->opc == OPC_META_FO)
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dst->regs[1]->instr->regs[0]->flags |= IR3_REG_HALF;
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}
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}
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if (!dst->is_ssa) {
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nir_register *reg = dst->reg.reg;
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struct ir3_array *arr = ir3_get_array(ctx, reg);
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unsigned num_components = ctx->last_dst_n;
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struct ir3_instruction *addr = NULL;
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if (dst->reg.indirect)
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addr = ir3_get_addr(ctx, ir3_get_src(ctx, dst->reg.indirect)[0],
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reg->num_components);
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for (unsigned i = 0; i < num_components; i++) {
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unsigned n = dst->reg.base_offset * reg->num_components + i;
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compile_assert(ctx, n < arr->length);
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if (!ctx->last_dst[i])
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continue;
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ir3_create_array_store(ctx, arr, n, ctx->last_dst[i], addr);
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}
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ralloc_free(ctx->last_dst);
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}
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ctx->last_dst = NULL;
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ctx->last_dst_n = 0;
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}
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struct ir3_instruction *
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ir3_create_collect(struct ir3_context *ctx, struct ir3_instruction *const *arr,
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unsigned arrsz)
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{
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struct ir3_block *block = ctx->block;
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struct ir3_instruction *collect;
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if (arrsz == 0)
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return NULL;
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unsigned flags = arr[0]->regs[0]->flags & IR3_REG_HALF;
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collect = ir3_instr_create2(block, OPC_META_FI, 1 + arrsz);
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ir3_reg_create(collect, 0, flags); /* dst */
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for (unsigned i = 0; i < arrsz; i++) {
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struct ir3_instruction *elem = arr[i];
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/* Since arrays are pre-colored in RA, we can't assume that
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* things will end up in the right place. (Ie. if a collect
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* joins elements from two different arrays.) So insert an
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* extra mov.
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*
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* We could possibly skip this if all the collected elements
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* are contiguous elements in a single array.. not sure how
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* likely that is to happen.
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*
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* Fixes a problem with glamor shaders, that in effect do
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* something like:
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*
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* if (foo)
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* texcoord = ..
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* else
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* texcoord = ..
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* color = texture2D(tex, texcoord);
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*
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* In this case, texcoord will end up as nir registers (which
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* translate to ir3 array's of length 1. And we can't assume
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* the two (or more) arrays will get allocated in consecutive
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* scalar registers.
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*
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*/
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if (elem->regs[0]->flags & IR3_REG_ARRAY) {
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type_t type = (flags & IR3_REG_HALF) ? TYPE_U16 : TYPE_U32;
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elem = ir3_MOV(block, elem, type);
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}
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compile_assert(ctx, (elem->regs[0]->flags & IR3_REG_HALF) == flags);
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ir3_reg_create(collect, 0, IR3_REG_SSA | flags)->instr = elem;
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}
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return collect;
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}
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/* helper for instructions that produce multiple consecutive scalar
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* outputs which need to have a split/fanout meta instruction inserted
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*/
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void
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ir3_split_dest(struct ir3_block *block, struct ir3_instruction **dst,
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struct ir3_instruction *src, unsigned base, unsigned n)
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{
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struct ir3_instruction *prev = NULL;
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if ((n == 1) && (src->regs[0]->wrmask == 0x1)) {
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dst[0] = src;
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return;
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}
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for (int i = 0, j = 0; i < n; i++) {
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struct ir3_instruction *split = ir3_instr_create(block, OPC_META_FO);
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ir3_reg_create(split, 0, IR3_REG_SSA);
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ir3_reg_create(split, 0, IR3_REG_SSA)->instr = src;
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split->fo.off = i + base;
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if (prev) {
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split->cp.left = prev;
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split->cp.left_cnt++;
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prev->cp.right = split;
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prev->cp.right_cnt++;
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}
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prev = split;
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if (src->regs[0]->wrmask & (1 << (i + base)))
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dst[j++] = split;
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}
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}
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void
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ir3_context_error(struct ir3_context *ctx, const char *format, ...)
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{
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struct hash_table *errors = NULL;
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va_list ap;
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va_start(ap, format);
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if (ctx->cur_instr) {
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errors = _mesa_hash_table_create(NULL,
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_mesa_hash_pointer,
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_mesa_key_pointer_equal);
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char *msg = ralloc_vasprintf(errors, format, ap);
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_mesa_hash_table_insert(errors, ctx->cur_instr, msg);
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} else {
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_debug_vprintf(format, ap);
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||||
}
|
||||
va_end(ap);
|
||||
nir_print_shader_annotated(ctx->s, stdout, errors);
|
||||
ralloc_free(errors);
|
||||
ctx->error = true;
|
||||
debug_assert(0);
|
||||
}
|
||||
|
||||
static struct ir3_instruction *
|
||||
create_addr(struct ir3_block *block, struct ir3_instruction *src, int align)
|
||||
{
|
||||
struct ir3_instruction *instr, *immed;
|
||||
|
||||
/* TODO in at least some cases, the backend could probably be
|
||||
* made clever enough to propagate IR3_REG_HALF..
|
||||
*/
|
||||
instr = ir3_COV(block, src, TYPE_U32, TYPE_S16);
|
||||
instr->regs[0]->flags |= IR3_REG_HALF;
|
||||
|
||||
switch(align){
|
||||
case 1:
|
||||
/* src *= 1: */
|
||||
break;
|
||||
case 2:
|
||||
/* src *= 2 => src <<= 1: */
|
||||
immed = create_immed(block, 1);
|
||||
immed->regs[0]->flags |= IR3_REG_HALF;
|
||||
|
||||
instr = ir3_SHL_B(block, instr, 0, immed, 0);
|
||||
instr->regs[0]->flags |= IR3_REG_HALF;
|
||||
instr->regs[1]->flags |= IR3_REG_HALF;
|
||||
break;
|
||||
case 3:
|
||||
/* src *= 3: */
|
||||
immed = create_immed(block, 3);
|
||||
immed->regs[0]->flags |= IR3_REG_HALF;
|
||||
|
||||
instr = ir3_MULL_U(block, instr, 0, immed, 0);
|
||||
instr->regs[0]->flags |= IR3_REG_HALF;
|
||||
instr->regs[1]->flags |= IR3_REG_HALF;
|
||||
break;
|
||||
case 4:
|
||||
/* src *= 4 => src <<= 2: */
|
||||
immed = create_immed(block, 2);
|
||||
immed->regs[0]->flags |= IR3_REG_HALF;
|
||||
|
||||
instr = ir3_SHL_B(block, instr, 0, immed, 0);
|
||||
instr->regs[0]->flags |= IR3_REG_HALF;
|
||||
instr->regs[1]->flags |= IR3_REG_HALF;
|
||||
break;
|
||||
default:
|
||||
unreachable("bad align");
|
||||
return NULL;
|
||||
}
|
||||
|
||||
instr = ir3_MOV(block, instr, TYPE_S16);
|
||||
instr->regs[0]->num = regid(REG_A0, 0);
|
||||
instr->regs[0]->flags |= IR3_REG_HALF;
|
||||
instr->regs[1]->flags |= IR3_REG_HALF;
|
||||
|
||||
return instr;
|
||||
}
|
||||
|
||||
/* caches addr values to avoid generating multiple cov/shl/mova
|
||||
* sequences for each use of a given NIR level src as address
|
||||
*/
|
||||
struct ir3_instruction *
|
||||
ir3_get_addr(struct ir3_context *ctx, struct ir3_instruction *src, int align)
|
||||
{
|
||||
struct ir3_instruction *addr;
|
||||
unsigned idx = align - 1;
|
||||
|
||||
compile_assert(ctx, idx < ARRAY_SIZE(ctx->addr_ht));
|
||||
|
||||
if (!ctx->addr_ht[idx]) {
|
||||
ctx->addr_ht[idx] = _mesa_hash_table_create(ctx,
|
||||
_mesa_hash_pointer, _mesa_key_pointer_equal);
|
||||
} else {
|
||||
struct hash_entry *entry;
|
||||
entry = _mesa_hash_table_search(ctx->addr_ht[idx], src);
|
||||
if (entry)
|
||||
return entry->data;
|
||||
}
|
||||
|
||||
addr = create_addr(ctx->block, src, align);
|
||||
_mesa_hash_table_insert(ctx->addr_ht[idx], src, addr);
|
||||
|
||||
return addr;
|
||||
}
|
||||
|
||||
struct ir3_instruction *
|
||||
ir3_get_predicate(struct ir3_context *ctx, struct ir3_instruction *src)
|
||||
{
|
||||
struct ir3_block *b = ctx->block;
|
||||
struct ir3_instruction *cond;
|
||||
|
||||
/* NOTE: only cmps.*.* can write p0.x: */
|
||||
cond = ir3_CMPS_S(b, src, 0, create_immed(b, 0), 0);
|
||||
cond->cat2.condition = IR3_COND_NE;
|
||||
|
||||
/* condition always goes in predicate register: */
|
||||
cond->regs[0]->num = regid(REG_P0, 0);
|
||||
|
||||
return cond;
|
||||
}
|
||||
|
||||
/*
|
||||
* Array helpers
|
||||
*/
|
||||
|
||||
void
|
||||
ir3_declare_array(struct ir3_context *ctx, nir_register *reg)
|
||||
{
|
||||
struct ir3_array *arr = rzalloc(ctx, struct ir3_array);
|
||||
arr->id = ++ctx->num_arrays;
|
||||
/* NOTE: sometimes we get non array regs, for example for arrays of
|
||||
* length 1. See fs-const-array-of-struct-of-array.shader_test. So
|
||||
* treat a non-array as if it was an array of length 1.
|
||||
*
|
||||
* It would be nice if there was a nir pass to convert arrays of
|
||||
* length 1 to ssa.
|
||||
*/
|
||||
arr->length = reg->num_components * MAX2(1, reg->num_array_elems);
|
||||
compile_assert(ctx, arr->length > 0);
|
||||
arr->r = reg;
|
||||
list_addtail(&arr->node, &ctx->ir->array_list);
|
||||
}
|
||||
|
||||
struct ir3_array *
|
||||
ir3_get_array(struct ir3_context *ctx, nir_register *reg)
|
||||
{
|
||||
list_for_each_entry (struct ir3_array, arr, &ctx->ir->array_list, node) {
|
||||
if (arr->r == reg)
|
||||
return arr;
|
||||
}
|
||||
ir3_context_error(ctx, "bogus reg: %s\n", reg->name);
|
||||
return NULL;
|
||||
}
|
||||
|
||||
/* relative (indirect) if address!=NULL */
|
||||
struct ir3_instruction *
|
||||
ir3_create_array_load(struct ir3_context *ctx, struct ir3_array *arr, int n,
|
||||
struct ir3_instruction *address)
|
||||
{
|
||||
struct ir3_block *block = ctx->block;
|
||||
struct ir3_instruction *mov;
|
||||
struct ir3_register *src;
|
||||
|
||||
mov = ir3_instr_create(block, OPC_MOV);
|
||||
mov->cat1.src_type = TYPE_U32;
|
||||
mov->cat1.dst_type = TYPE_U32;
|
||||
mov->barrier_class = IR3_BARRIER_ARRAY_R;
|
||||
mov->barrier_conflict = IR3_BARRIER_ARRAY_W;
|
||||
ir3_reg_create(mov, 0, 0);
|
||||
src = ir3_reg_create(mov, 0, IR3_REG_ARRAY |
|
||||
COND(address, IR3_REG_RELATIV));
|
||||
src->instr = arr->last_write;
|
||||
src->size = arr->length;
|
||||
src->array.id = arr->id;
|
||||
src->array.offset = n;
|
||||
|
||||
if (address)
|
||||
ir3_instr_set_address(mov, address);
|
||||
|
||||
return mov;
|
||||
}
|
||||
|
||||
/* relative (indirect) if address!=NULL */
|
||||
void
|
||||
ir3_create_array_store(struct ir3_context *ctx, struct ir3_array *arr, int n,
|
||||
struct ir3_instruction *src, struct ir3_instruction *address)
|
||||
{
|
||||
struct ir3_block *block = ctx->block;
|
||||
struct ir3_instruction *mov;
|
||||
struct ir3_register *dst;
|
||||
|
||||
/* if not relative store, don't create an extra mov, since that
|
||||
* ends up being difficult for cp to remove.
|
||||
*/
|
||||
if (!address) {
|
||||
dst = src->regs[0];
|
||||
|
||||
src->barrier_class |= IR3_BARRIER_ARRAY_W;
|
||||
src->barrier_conflict |= IR3_BARRIER_ARRAY_R | IR3_BARRIER_ARRAY_W;
|
||||
|
||||
dst->flags |= IR3_REG_ARRAY;
|
||||
dst->instr = arr->last_write;
|
||||
dst->size = arr->length;
|
||||
dst->array.id = arr->id;
|
||||
dst->array.offset = n;
|
||||
|
||||
arr->last_write = src;
|
||||
|
||||
array_insert(block, block->keeps, src);
|
||||
|
||||
return;
|
||||
}
|
||||
|
||||
mov = ir3_instr_create(block, OPC_MOV);
|
||||
mov->cat1.src_type = TYPE_U32;
|
||||
mov->cat1.dst_type = TYPE_U32;
|
||||
mov->barrier_class = IR3_BARRIER_ARRAY_W;
|
||||
mov->barrier_conflict = IR3_BARRIER_ARRAY_R | IR3_BARRIER_ARRAY_W;
|
||||
dst = ir3_reg_create(mov, 0, IR3_REG_ARRAY |
|
||||
COND(address, IR3_REG_RELATIV));
|
||||
dst->instr = arr->last_write;
|
||||
dst->size = arr->length;
|
||||
dst->array.id = arr->id;
|
||||
dst->array.offset = n;
|
||||
ir3_reg_create(mov, 0, IR3_REG_SSA)->instr = src;
|
||||
|
||||
if (address)
|
||||
ir3_instr_set_address(mov, address);
|
||||
|
||||
arr->last_write = mov;
|
||||
|
||||
/* the array store may only matter to something in an earlier
|
||||
* block (ie. loops), but since arrays are not in SSA, depth
|
||||
* pass won't know this.. so keep all array stores:
|
||||
*/
|
||||
array_insert(block, block->keeps, mov);
|
||||
}
|
||||
178
src/freedreno/ir3/ir3_context.h
Normal file
178
src/freedreno/ir3/ir3_context.h
Normal file
|
|
@ -0,0 +1,178 @@
|
|||
/*
|
||||
* Copyright (C) 2015-2018 Rob Clark <robclark@freedesktop.org>
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining a
|
||||
* copy of this software and associated documentation files (the "Software"),
|
||||
* to deal in the Software without restriction, including without limitation
|
||||
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
|
||||
* and/or sell copies of the Software, and to permit persons to whom the
|
||||
* Software is furnished to do so, subject to the following conditions:
|
||||
*
|
||||
* The above copyright notice and this permission notice (including the next
|
||||
* paragraph) shall be included in all copies or substantial portions of the
|
||||
* Software.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
||||
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
|
||||
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
|
||||
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
|
||||
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
|
||||
* SOFTWARE.
|
||||
*
|
||||
* Authors:
|
||||
* Rob Clark <robclark@freedesktop.org>
|
||||
*/
|
||||
|
||||
#ifndef IR3_CONTEXT_H_
|
||||
#define IR3_CONTEXT_H_
|
||||
|
||||
#include "ir3_nir.h"
|
||||
#include "ir3.h"
|
||||
|
||||
/* for conditionally setting boolean flag(s): */
|
||||
#define COND(bool, val) ((bool) ? (val) : 0)
|
||||
|
||||
#define DBG(fmt, ...) \
|
||||
do { debug_printf("%s:%d: "fmt "\n", \
|
||||
__FUNCTION__, __LINE__, ##__VA_ARGS__); } while (0)
|
||||
|
||||
/**
|
||||
* The context for compilation of a single shader.
|
||||
*/
|
||||
struct ir3_context {
|
||||
struct ir3_compiler *compiler;
|
||||
|
||||
struct nir_shader *s;
|
||||
|
||||
struct nir_instr *cur_instr; /* current instruction, just for debug */
|
||||
|
||||
struct ir3 *ir;
|
||||
struct ir3_shader_variant *so;
|
||||
|
||||
struct ir3_block *block; /* the current block */
|
||||
struct ir3_block *in_block; /* block created for shader inputs */
|
||||
|
||||
nir_function_impl *impl;
|
||||
|
||||
/* For fragment shaders, varyings are not actual shader inputs,
|
||||
* instead the hw passes a varying-coord which is used with
|
||||
* bary.f.
|
||||
*
|
||||
* But NIR doesn't know that, it still declares varyings as
|
||||
* inputs. So we do all the input tracking normally and fix
|
||||
* things up after compile_instructions()
|
||||
*
|
||||
* NOTE that frag_vcoord is the hardware position (possibly it
|
||||
* is actually an index or tag or some such.. it is *not*
|
||||
* values that can be directly used for gl_FragCoord..)
|
||||
*/
|
||||
struct ir3_instruction *frag_vcoord;
|
||||
|
||||
/* for fragment shaders, for gl_FrontFacing and gl_FragCoord: */
|
||||
struct ir3_instruction *frag_face, *frag_coord;
|
||||
|
||||
/* For vertex shaders, keep track of the system values sources */
|
||||
struct ir3_instruction *vertex_id, *basevertex, *instance_id;
|
||||
|
||||
/* For fragment shaders: */
|
||||
struct ir3_instruction *samp_id, *samp_mask_in;
|
||||
|
||||
/* Compute shader inputs: */
|
||||
struct ir3_instruction *local_invocation_id, *work_group_id;
|
||||
|
||||
/* mapping from nir_register to defining instruction: */
|
||||
struct hash_table *def_ht;
|
||||
|
||||
unsigned num_arrays;
|
||||
|
||||
/* a common pattern for indirect addressing is to request the
|
||||
* same address register multiple times. To avoid generating
|
||||
* duplicate instruction sequences (which our backend does not
|
||||
* try to clean up, since that should be done as the NIR stage)
|
||||
* we cache the address value generated for a given src value:
|
||||
*
|
||||
* Note that we have to cache these per alignment, since same
|
||||
* src used for an array of vec1 cannot be also used for an
|
||||
* array of vec4.
|
||||
*/
|
||||
struct hash_table *addr_ht[4];
|
||||
|
||||
/* last dst array, for indirect we need to insert a var-store.
|
||||
*/
|
||||
struct ir3_instruction **last_dst;
|
||||
unsigned last_dst_n;
|
||||
|
||||
/* maps nir_block to ir3_block, mostly for the purposes of
|
||||
* figuring out the blocks successors
|
||||
*/
|
||||
struct hash_table *block_ht;
|
||||
|
||||
/* on a4xx, bitmask of samplers which need astc+srgb workaround: */
|
||||
unsigned astc_srgb;
|
||||
|
||||
unsigned samples; /* bitmask of x,y sample shifts */
|
||||
|
||||
unsigned max_texture_index;
|
||||
|
||||
/* set if we encounter something we can't handle yet, so we
|
||||
* can bail cleanly and fallback to TGSI compiler f/e
|
||||
*/
|
||||
bool error;
|
||||
};
|
||||
|
||||
struct ir3_context * ir3_context_init(struct ir3_compiler *compiler,
|
||||
struct ir3_shader_variant *so);
|
||||
void ir3_context_free(struct ir3_context *ctx);
|
||||
|
||||
/* gpu pointer size in units of 32bit registers/slots */
|
||||
static inline
|
||||
unsigned ir3_pointer_size(struct ir3_context *ctx)
|
||||
{
|
||||
return (ctx->compiler->gpu_id >= 500) ? 2 : 1;
|
||||
}
|
||||
|
||||
struct ir3_instruction ** ir3_get_dst_ssa(struct ir3_context *ctx, nir_ssa_def *dst, unsigned n);
|
||||
struct ir3_instruction ** ir3_get_dst(struct ir3_context *ctx, nir_dest *dst, unsigned n);
|
||||
struct ir3_instruction * const * ir3_get_src(struct ir3_context *ctx, nir_src *src);
|
||||
void put_dst(struct ir3_context *ctx, nir_dest *dst);
|
||||
struct ir3_instruction * ir3_create_collect(struct ir3_context *ctx,
|
||||
struct ir3_instruction *const *arr, unsigned arrsz);
|
||||
void ir3_split_dest(struct ir3_block *block, struct ir3_instruction **dst,
|
||||
struct ir3_instruction *src, unsigned base, unsigned n);
|
||||
|
||||
void ir3_context_error(struct ir3_context *ctx, const char *format, ...);
|
||||
|
||||
#define compile_assert(ctx, cond) do { \
|
||||
if (!(cond)) ir3_context_error((ctx), "failed assert: "#cond"\n"); \
|
||||
} while (0)
|
||||
|
||||
struct ir3_instruction * ir3_get_addr(struct ir3_context *ctx,
|
||||
struct ir3_instruction *src, int align);
|
||||
struct ir3_instruction * ir3_get_predicate(struct ir3_context *ctx,
|
||||
struct ir3_instruction *src);
|
||||
|
||||
void ir3_declare_array(struct ir3_context *ctx, nir_register *reg);
|
||||
struct ir3_array * ir3_get_array(struct ir3_context *ctx, nir_register *reg);
|
||||
struct ir3_instruction *ir3_create_array_load(struct ir3_context *ctx,
|
||||
struct ir3_array *arr, int n, struct ir3_instruction *address);
|
||||
void ir3_create_array_store(struct ir3_context *ctx, struct ir3_array *arr, int n,
|
||||
struct ir3_instruction *src, struct ir3_instruction *address);
|
||||
|
||||
static inline type_t utype_for_size(unsigned bit_size)
|
||||
{
|
||||
switch (bit_size) {
|
||||
case 32: return TYPE_U32;
|
||||
case 16: return TYPE_U16;
|
||||
case 8: return TYPE_U8;
|
||||
default: unreachable("bad bitsize"); return ~0;
|
||||
}
|
||||
}
|
||||
|
||||
static inline type_t utype_src(nir_src src)
|
||||
{ return utype_for_size(nir_src_bit_size(src)); }
|
||||
|
||||
static inline type_t utype_dst(nir_dest dst)
|
||||
{ return utype_for_size(nir_dest_bit_size(dst)); }
|
||||
|
||||
#endif /* IR3_CONTEXT_H_ */
|
||||
|
|
@ -37,6 +37,8 @@ libfreedreno_ir3_files = files(
|
|||
'ir3_compiler_nir.c',
|
||||
'ir3_compiler.c',
|
||||
'ir3_compiler.h',
|
||||
'ir3_context.c',
|
||||
'ir3_context.h',
|
||||
'ir3_cp.c',
|
||||
'ir3_depth.c',
|
||||
'ir3_group.c',
|
||||
|
|
|
|||
Loading…
Add table
Reference in a new issue