mesa/src/amd
Zan Dobersek 7fd5f76393 nir/lower_vars_to_scratch: calculate threshold-limited variable size separately
ir3's lowering of variables to scratch memory has to treat 8-bit values as
16-bit ones when comparing such value's size against the given threshold
since those values are handled through 16-bit half-registers. But those
values can still use natural 8-bit size and alignment for storing inside
scratch memory.

nir_lower_vars_to_scratch now accepts two size-and-alignment functions,
one used for calculating the variable size and the other for calculating
the size and alignment needed for storing inside scratch memory. Non-ir3
uses of this pass can just duplicate the currently-used function. ir3
provides a separate variable-size function that special-cases 8-bit types.

Signed-off-by: Zan Dobersek <zdobersek@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29875>
2024-08-07 14:32:28 +00:00
..
addrlib amd: add GFX v11.5.2 support 2024-07-02 12:05:23 +00:00
ci Uprev Piglit to 4a62c26721a47552a96416a134b789a813dd51a6 2024-08-05 10:45:38 +00:00
common nir/lower_vars_to_scratch: calculate threshold-limited variable size separately 2024-08-07 14:32:28 +00:00
compiler aco: test xor swap16 path 2024-08-06 20:40:12 +00:00
drm-shim build: pass licensing information in SPDX form 2024-06-29 12:42:49 -07:00
llvm nir: add nir_intrinsic_load_per_primitive_input, split from io_semantics flag 2024-07-23 16:13:16 +00:00
registers amd: add gfx12 register definitions 2024-05-11 22:14:05 -04:00
vpelib amd/vpelib: support VPE IP v6.1.3 2024-07-02 12:05:23 +00:00
vulkan radv/rt: remove one VALU from traversal loop 2024-07-25 20:24:23 +00:00
meson.build build: pass licensing information in SPDX form 2024-06-29 12:42:49 -07:00