mesa/src/intel
Francisco Jerez f0b6348ad0 intel/eu/gfx8-9: Fix execution with all channels disabled due to HW bug #220160235.
This hardware bug is the result of a control flow optimization present
in Gfx8-9 meant to prevent the ELSE instruction from disabling all
channels and update the control flow stack only to have them
re-enabled at the ENDIF instruction executed immediately after it.
Instead, on Gfx8-9 an ELSE instruction that would normally have ended
up with all channels disabled would pop off the last element of the
stack and jump directly to JIP+1 instead of to the ENDIF at JIP,
skipping over the ENDIF instruction.  In simple cases this would work
okay (though it's actual performance benefit is questionable), but in
cases where a branch instruction within the IF block (e.g. BREAK or
CONTINUE) caused all active channels to jump outside the IF
conditional, the optimization would break the JIP chain of "join"
instructions by skipping the ENDIF, causing the block of instructions
immediately after the ENDIF to execute with all channels disabled
until execution reaches the reconvergence point.

This issue was observed on SKL in the
dEQP-VK.reconvergence.subgroup_uniform_control_flow_elect.compute.nesting4.0.38
test in combination with some Vulkan binding model changes Lionel is
working on.  In such cases the execution with all channels disabled
was leading to corruption of an indirect message descriptor, causing a
hang.

Unfortunately the hardware bug doesn't provide a recommended
workaround.  In order to fix the problem we point the JIP of an ELSE
instruction to the instruction immediately before the ENDIF -- However
that's not expected to work due to the restriction that JIP and UIP
must be equal if and only if BranchCtrl is disabled -- So this patch
also enables BranchCtrl, which is intended to support join
instructions within the "ELSE" block, which in turn disables the
optimization described above, which in turn causes us to execute the
instruction immediately *before* the ENDIF with all channels disabled
-- So in order to avoid further fallout from executing code with all
channels disabled we need to insert a NOP before ENDIF instructions
that have a matching ELSE instruction.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20921>
2023-02-07 21:37:12 +00:00
..
blorp intel/compiler: Convert wm_prog_key::multisample_fbo to a tri-state 2023-02-06 09:12:18 +00:00
ci anv: expose EXT_load_store_op_none 2023-02-01 12:53:29 +00:00
common intel/fs: Make per-sample and coarse dispatch tri-state 2023-02-06 09:12:18 +00:00
compiler intel/eu/gfx8-9: Fix execution with all channels disabled due to HW bug #220160235. 2023-02-07 21:37:12 +00:00
dev intel/dev: remove invalid EHL pci id 2023-02-06 16:48:39 +00:00
ds intel/ds: track end of pipe bits 2023-02-06 09:12:18 +00:00
genxml intel/genxml/gen125: Tune 3DSTATE_WM Walker direction 2023-02-07 07:34:44 -08:00
isl intel/isl: Disable CCS on MTL until B0 (Wa_14017353530) 2022-12-15 11:43:00 -08:00
nullhw-layer utils: Merge util/debug.* into util/u_debug.* and remove util/debug.* 2022-11-02 07:25:39 +00:00
perf intel: add MTL performance metrics 2022-12-09 09:13:02 +00:00
tools anv,hasvk: migrate align32 to the right functions from util 2023-01-06 17:22:16 +00:00
vulkan anv: use malloc for host only descriptor sets 2023-02-07 07:28:32 +00:00
vulkan_hasvk intel/fs: make alpha_to_coverage a tristate 2023-02-06 09:12:18 +00:00
meson.build intel: Disable SSE2 instruction set if building for non x86 architectures 2022-11-23 16:57:23 +00:00