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98cd68ec05
radeonsi will export texture with these modifiers. piglit tests: spec@ext_image_dma_buf_import@ext_image_dma_buf_import-export-tex spec@ext_image_dma_buf_import@ext_image_dma_buf_import-tex-modifier Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com> Reviewed-by: Marek Olšák <marek.olsak@amd.com> Acked-by: Daniel Stone <daniels@collabora.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31658>
72 lines
2.7 KiB
C
72 lines
2.7 KiB
C
/*
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* Copyright © 2021 Advanced Micro Devices, Inc.
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*
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* SPDX-License-Identifier: MIT
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*/
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#ifndef AC_DRM_FOURCC_H
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#define AC_DRM_FOURCC_H
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#ifdef _WIN32
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#include <stdint.h>
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typedef uint64_t __u64;
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#define DRM_FORMAT_MOD_VENDOR_NONE 0
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#define DRM_FORMAT_MOD_VENDOR_AMD 0x02
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#define DRM_FORMAT_RESERVED ((1ULL << 56) - 1)
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#define fourcc_mod_code(vendor, val) \
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((((__u64)DRM_FORMAT_MOD_VENDOR_## vendor) << 56) | ((val) & 0x00ffffffffffffffULL))
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#define DRM_FORMAT_MOD_INVALID fourcc_mod_code(NONE, DRM_FORMAT_RESERVED)
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#define DRM_FORMAT_MOD_LINEAR fourcc_mod_code(NONE, 0)
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#define AMD_FMT_MOD fourcc_mod_code(AMD, 0)
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#define IS_AMD_FMT_MOD(val) (((val) >> 56) == DRM_FORMAT_MOD_VENDOR_AMD)
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#define AMD_FMT_MOD_TILE_VER_GFX9 1
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#define AMD_FMT_MOD_TILE_VER_GFX10 2
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#define AMD_FMT_MOD_TILE_VER_GFX10_RBPLUS 3
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#define AMD_FMT_MOD_TILE_VER_GFX11 4
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#define AMD_FMT_MOD_TILE_VER_GFX12 5
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#define AMD_FMT_MOD_TILE_GFX9_64K_S 9
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#define AMD_FMT_MOD_TILE_GFX9_64K_D 10
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#define AMD_FMT_MOD_TILE_GFX9_4K_D_X 22
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#define AMD_FMT_MOD_TILE_GFX9_64K_S_X 25
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#define AMD_FMT_MOD_TILE_GFX9_64K_D_X 26
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#define AMD_FMT_MOD_TILE_GFX9_64K_R_X 27
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#define AMD_FMT_MOD_TILE_GFX11_256K_R_X 31
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#define AMD_FMT_MOD_TILE_GFX12_256B_2D 1
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#define AMD_FMT_MOD_TILE_GFX12_4K_2D 2
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#define AMD_FMT_MOD_TILE_GFX12_64K_2D 3
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#define AMD_FMT_MOD_TILE_GFX12_256K_2D 4
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#define AMD_FMT_MOD_DCC_BLOCK_64B 0
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#define AMD_FMT_MOD_DCC_BLOCK_128B 1
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#define AMD_FMT_MOD_DCC_BLOCK_256B 2
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#define AMD_FMT_MOD_TILE_VERSION_SHIFT 0
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#define AMD_FMT_MOD_TILE_VERSION_MASK 0xFF
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#define AMD_FMT_MOD_TILE_SHIFT 8
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#define AMD_FMT_MOD_TILE_MASK 0x1F
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#define AMD_FMT_MOD_DCC_SHIFT 13
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#define AMD_FMT_MOD_DCC_MASK 0x1
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#define AMD_FMT_MOD_DCC_RETILE_SHIFT 14
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#define AMD_FMT_MOD_DCC_RETILE_MASK 0x1
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#define AMD_FMT_MOD_DCC_PIPE_ALIGN_SHIFT 15
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#define AMD_FMT_MOD_DCC_PIPE_ALIGN_MASK 0x1
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#define AMD_FMT_MOD_DCC_INDEPENDENT_64B_SHIFT 16
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#define AMD_FMT_MOD_DCC_INDEPENDENT_64B_MASK 0x1
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#define AMD_FMT_MOD_DCC_INDEPENDENT_128B_SHIFT 17
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#define AMD_FMT_MOD_DCC_INDEPENDENT_128B_MASK 0x1
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#define AMD_FMT_MOD_DCC_MAX_COMPRESSED_BLOCK_SHIFT 18
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#define AMD_FMT_MOD_DCC_MAX_COMPRESSED_BLOCK_MASK 0x3
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#define AMD_FMT_MOD_DCC_CONSTANT_ENCODE_SHIFT 20
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#define AMD_FMT_MOD_PIPE_XOR_BITS_SHIFT 21
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#define AMD_FMT_MOD_BANK_XOR_BITS_SHIFT 24
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#define AMD_FMT_MOD_PACKERS_SHIFT 27 /* aliases with BANK_XOR_BITS */
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#define AMD_FMT_MOD_RB_SHIFT 30
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#define AMD_FMT_MOD_RB_MASK 0x7
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#define AMD_FMT_MOD_PIPE_SHIFT 33
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#define AMD_FMT_MOD_SET(field, value) \
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((uint64_t)(value) << AMD_FMT_MOD_##field##_SHIFT)
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#define AMD_FMT_MOD_GET(field, value) \
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(((value) >> AMD_FMT_MOD_##field##_SHIFT) & AMD_FMT_MOD_##field##_MASK)
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#else
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#include "drm-uapi/drm_fourcc.h"
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#endif
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#endif /* AC_DRM_FOURCC_H */
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