Francisco Jerez 58324389be intel/fs: Take into account amount of data read in spilling cost heuristic. ... Until now the spilling cost calculation was neglecting the amount of data read from the register during the spilling cost calculation. This caused it to make suboptimal decisions in some cases leading to higher memory bandwidth usage than necessary. Improves Unigine Heaven performance by ~4% on BDW, reversing an unintended FPS regression from my previous commit 147e71242c with n=12 and statistical significance 5%. In addition SynMark2 OglCSDof performance is improved by an additional ~5% on SKL, and a Kerbal Space Program apitrace around the Moho planet I can provide on request improves by ~20%. Cc: <mesa-stable@lists.freedesktop.org> Reviewed-by: Plamena Manolova <plamena.manolova@intel.com> Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>		2017-04-24 11:01:40 -07:00
..
.gitignore
brw_cfg.cpp
brw_cfg.h	intel/compiler: consistently use ifndef guards over pragma once	2017-03-22 16:55:22 +00:00
brw_compiler.c
brw_compiler.h	anv/pipeline: make FragCoord include sample positions when sample shading	2017-03-24 08:11:53 +01:00
brw_dead_control_flow.cpp
brw_dead_control_flow.h	intel/compiler: consistently use ifndef guards over pragma once	2017-03-22 16:55:22 +00:00
brw_disasm.c	i965/disasm: also print nibctrl in IVB for execsize=8	2017-04-14 14:56:06 -07:00
brw_eu.c
brw_eu.h
brw_eu_compact.c
brw_eu_defines.h	i965/vec4: split VEC4_OPCODE_FROM_DOUBLE into one opcode per destination's type	2017-04-14 14:56:08 -07:00
brw_eu_emit.c	i965: Use correct VertStride on align16 instructions.	2017-04-14 14:56:09 -07:00
brw_eu_util.c	intel/compiler: whitespace cleanups	2017-03-13 11:16:35 +00:00
brw_eu_validate.c	i965: Handle IVB DF differences in the validator.	2017-04-14 14:56:07 -07:00
brw_fs.cpp	i965/fs: lower all non-force_writemask_all DF instructions to SIMD4 on IVB/BYT	2017-04-14 14:56:08 -07:00
brw_fs.h	i965/fs: rename lower_d2x to lower_conversions	2017-04-14 14:56:07 -07:00
brw_fs_builder.h
brw_fs_cmod_propagation.cpp
brw_fs_combine_constants.cpp
brw_fs_copy_propagation.cpp
brw_fs_cse.cpp
brw_fs_dead_code_eliminate.cpp
brw_fs_generator.cpp	i965/fs: Get 64-bit indirect moves working on IVB.	2017-04-14 14:56:08 -07:00
brw_fs_live_variables.cpp
brw_fs_live_variables.h	intel/compiler: consistently use ifndef guards over pragma once	2017-03-22 16:55:22 +00:00
brw_fs_lower_conversions.cpp	i965/fs: rename lower_d2x to lower_conversions	2017-04-14 14:56:07 -07:00
brw_fs_lower_pack.cpp
brw_fs_nir.cpp	i965/fs: Always provide a default LOD of 0 for TXS and TXL	2017-04-04 18:33:35 -07:00
brw_fs_reg_allocate.cpp	intel/fs: Take into account amount of data read in spilling cost heuristic.	2017-04-24 11:01:40 -07:00
brw_fs_register_coalesce.cpp
brw_fs_saturate_propagation.cpp
brw_fs_sel_peephole.cpp	Revert "i965/fs: Don't emit SEL instructions for type-converting MOVs."	2017-04-14 14:56:07 -07:00
brw_fs_surface_builder.cpp	i965: Move the back-end compiler to src/intel/compiler	2017-03-13 11:16:34 +00:00
brw_fs_surface_builder.h
brw_fs_validate.cpp
brw_fs_visitor.cpp
brw_inst.h
brw_interpolation_map.c
brw_ir_allocator.h
brw_ir_fs.h	i965/fs: add helper to retrieve instruction execution type	2017-04-14 14:56:07 -07:00
brw_ir_vec4.h	i965/vec4: don't do horizontal stride on some register file types	2017-04-14 14:56:09 -07:00
brw_nir.c	nir/i965: add before ffma algebraic opts	2017-04-24 12:08:14 +10:00
brw_nir.h	intel/compiler: consistently use ifndef guards over pragma once	2017-03-22 16:55:22 +00:00
brw_nir_analyze_boolean_resolves.c
brw_nir_attribute_workarounds.c	nir: Rework conversion opcodes	2017-03-14 07:36:40 -07:00
brw_nir_intrinsics.c
brw_nir_opt_peephole_ffma.c
brw_nir_tcs_workarounds.c
brw_nir_trig_workarounds.py
brw_packed_float.c
brw_predicated_break.cpp
brw_reg.h	i965/fs: add helper to retrieve instruction execution type	2017-04-14 14:56:07 -07:00
brw_schedule_instructions.cpp
brw_shader.cpp	i965/vec4: split VEC4_OPCODE_FROM_DOUBLE into one opcode per destination's type	2017-04-14 14:56:08 -07:00
brw_shader.h	intel/compiler: consistently use ifndef guards over pragma once	2017-03-22 16:55:22 +00:00
brw_vec4.cpp	i965/vec4: Use reads_accumulator_implicitly(), not MACH checks.	2017-04-24 10:53:49 -07:00
brw_vec4.h	i965/vec4: use vec4_builder to emit instructions in setup_imm_df()	2017-04-14 14:56:09 -07:00
brw_vec4_builder.h
brw_vec4_cmod_propagation.cpp
brw_vec4_copy_propagation.cpp	i965/vec4: split VEC4_OPCODE_FROM_DOUBLE into one opcode per destination's type	2017-04-14 14:56:08 -07:00
brw_vec4_cse.cpp
brw_vec4_dead_code_eliminate.cpp	i965/vec4/dce: improve track of partial flag register writes	2017-04-14 14:56:09 -07:00
brw_vec4_generator.cpp	i965/vec4: Fix exec size for MOVs {SET,PICK}_{HIGH,LOW}_32BIT.	2017-04-14 14:56:09 -07:00
brw_vec4_gs_nir.cpp
brw_vec4_gs_visitor.cpp
brw_vec4_gs_visitor.h
brw_vec4_live_variables.cpp
brw_vec4_live_variables.h	i965/vec4: consider subregister offset in live variables	2017-04-14 14:56:08 -07:00
brw_vec4_nir.cpp	i965/vec4: use vec4_builder to emit instructions in setup_imm_df()	2017-04-14 14:56:09 -07:00
brw_vec4_reg_allocate.cpp	i965/vec4: split VEC4_OPCODE_FROM_DOUBLE into one opcode per destination's type	2017-04-14 14:56:08 -07:00
brw_vec4_surface_builder.cpp
brw_vec4_surface_builder.h
brw_vec4_tcs.cpp
brw_vec4_tcs.h
brw_vec4_tes.cpp
brw_vec4_tes.h
brw_vec4_visitor.cpp
brw_vec4_vs.h
brw_vec4_vs_visitor.cpp
brw_vue_map.c
brw_wm_iz.cpp	intel/compiler: whitespace cleanups	2017-03-13 11:16:35 +00:00
gen6_gs_visitor.cpp
gen6_gs_visitor.h
intel_asm_annotation.c
intel_asm_annotation.h
test_eu_compact.cpp	intel/compiler: link all tests again gtest, even test_eu_compact"	2017-03-13 11:16:35 +00:00
test_eu_validate.cpp
test_fs_cmod_propagation.cpp
test_fs_copy_propagation.cpp
test_fs_saturate_propagation.cpp
test_vec4_cmod_propagation.cpp
test_vec4_copy_propagation.cpp
test_vec4_register_coalesce.cpp
test_vf_float_conversions.cpp