Lionel Landwerlin 64e8b0d255 anv: use the right dispatch size for tracing shaders ... We assumed the trampoline shader would always be SIMD8. Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com> Reviewed-by: Zhang, Jianxun <jianxun.zhang@intel.com> Acked-by: Caio Oliveira <caio.oliveira@intel.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16970>		2022-09-28 05:38:37 +00:00
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blorp	blorp: defined operations for debug purposes	2022-09-21 12:38:34 +00:00
ci	ci/intel: drop glmark2 terrain trace	2022-09-18 18:51:14 +00:00
common	intel/mi_builder: allow half GP registers for dereferencing	2022-09-28 05:38:36 +00:00
compiler	anv: disable SIMD16 for RT shaders	2022-09-28 05:38:37 +00:00
dev	intel/devinfo: Rename & implement num_dual_subslices	2022-09-28 05:38:36 +00:00
ds	intel/utrace: create the callback events for xfb trace points	2022-09-22 06:59:06 +00:00
genxml	anv: Set up the memory-backed FIFO buffer	2022-09-28 05:38:36 +00:00
isl	intel/utrace: make blorp tracepoints more readable	2022-09-21 12:38:34 +00:00
nullhw-layer	intel/nullhw: Use correct macro to fix build regression	2022-08-01 10:54:38 +00:00
perf	intel: fix typos found by codespell	2022-06-27 10:20:55 +00:00
tools	intel/tools: Also look for 'batch' tag	2022-08-17 02:24:09 +00:00
vulkan	anv: use the right dispatch size for tracing shaders	2022-09-28 05:38:37 +00:00
vulkan_hasvk	intel/dev: Adjust prefetch_size values for MTL engines	2022-09-22 02:14:47 +00:00
meson.build	intel: add a hasvk vulkan driver	2022-09-02 09:40:45 +00:00