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64bc538f5e
HW does not allow instructions with vector immediates to cross a GRF boundary if
it has a stride.
Under register pressure, the register allocator may place a temporary register
across such a boundary.
To resolve this, we now explicitly emit a MOV to upcast the UB payload into a
UW VGRF.
This ensures the SHR instruction operates on a dense, well-aligned region that
satisfies hardware alignment constraints.
Below is the portion of the shader exhibiting this issue:
Native code for unnamed fragment shader GLSL6 (src_hash 0x9c84a007) (sha1 48745e7dae90d08f8a9bbe4dbf837de23440c841f0344e669cb8af9df79bce58)
SIMD32 shader: 44 instructions. 0 loops. 354 cycles. 0:0 spills:fills, 2 sends, scheduled with mode latency-sensitive. Promoted 0 constants. GRF registers: 22. Non-SSA regs (after NIR): 11. Compacted 800 to 800 bytes (0%)
mov(1) f1<1>UW g0.30<0,1,0>UW { align1 WE_all 1N };
mov(1) f1.1<1>UW g1.30<0,1,0>UW { align1 WE_all 1N I@1 };
mov(32) g2<2>UW g0.20<2,8,0>UW { align1 WE_all };
mov(32) g4<2>UW g0.21<2,8,0>UW { align1 WE_all };
mov(32) g8<2>UW g1.20<2,8,0>UW { align1 WE_all };
mov(32) g10<2>UW g1.21<2,8,0>UW { align1 WE_all };
mov(16) g12<4>UB g0.60<1,8,0>UB { align1 1H };
mov(16) g13<4>UB g1.60<1,8,0>UB { align1 2H };
add(32) g0<1>UW g2<16,8,2>UW 0x01000100V { align1 WE_all I@6 };
add(32) g1<1>UW g4<16,8,2>UW 0x01010000V { align1 WE_all I@6 };
add(32) g2<1>UW g8<16,8,2>UW 0x01000100V { align1 WE_all I@6 };
add(32) g3<1>UW g10<16,8,2>UW 0x01010000V { align1 WE_all I@6 };
shr(16) g4<1>UW g12<32,8,4>UB 0x76543210V { align1 1H I@6 };
mov(16) g14.32<4>UB g13<32,8,4>UB { align1 2H I@6 };
sync nop(1) null<0,1,0>UB { align1 WE_all 1N I@6 };
mov(16) g5<1>UW g0<16,8,2>UW { align1 1H };
sync nop(1) null<0,1,0>UB { align1 WE_all 1N I@6 };
mov(16) g0<1>UW g1<16,8,2>UW { align1 1H };
sync nop(1) null<0,1,0>UB { align1 WE_all 5N I@6 };
mov(16) g5.16<1>UW g2<16,8,2>UW { align1 2H };
sync nop(1) null<0,1,0>UB { align1 WE_all 5N I@6 };
mov(16) g0.16<1>UW g3<16,8,2>UW { align1 2H };
shr(16) g4.16<1>UW g14.32<32,8,4>UB 0x76543210V { align1 2H I@5 };
ERROR: Invalid register region for source 0. See special restrictions section.
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/40856>
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`Mesa <https://mesa3d.org>`_ - The 3D Graphics Library ====================================================== Source ------ This repository lives at https://gitlab.freedesktop.org/mesa/mesa. Other repositories are likely forks, and code found there is not supported. Build & install --------------- You can find more information in our documentation (`docs/install.rst <https://docs.mesa3d.org/install.html>`_), but the recommended way is to use Meson (`docs/meson.rst <https://docs.mesa3d.org/meson.html>`_): .. code-block:: sh $ meson setup build $ ninja -C build/ $ sudo ninja -C build/ install Support ------- Many Mesa devs hang on IRC; if you're not sure which channel is appropriate, you should ask your question on `OFTC's #dri-devel <irc://irc.oftc.net/dri-devel>`_, someone will redirect you if necessary. Remember that not everyone is in the same timezone as you, so it might take a while before someone qualified sees your question. To figure out who you're talking to, or which nick to ping for your question, check out `Who's Who on IRC <https://dri.freedesktop.org/wiki/WhosWho/>`_. The next best option is to ask your question in an email to the mailing lists: `mesa-dev\@lists.freedesktop.org <https://lists.freedesktop.org/mailman/listinfo/mesa-dev>`_ Bug reports ----------- If you think something isn't working properly, please file a bug report (`docs/bugs.rst <https://docs.mesa3d.org/bugs.html>`_). Contributing ------------ Contributions are welcome, and step-by-step instructions can be found in our documentation (`docs/submittingpatches.rst <https://docs.mesa3d.org/submittingpatches.html>`_). Note that Mesa uses gitlab for patches submission, review and discussions.