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mesa/src/intel/compiler
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Ian Romanick 62795475e8 nir/algebraic: Distribute source modifiers into instructions 
There are three main classes of cases that are helped by this change:

1. When the negation is applied to a value being type converted (e.g.,
   float(-x)).  This could possibly also be handled with more clever
   code generation.

2. When the negation is applied to a phi node source (e.g., x = -(...);
   at the end of a basic block).  This was the original case that caught
   my attention while looking at shader-db dumps.

3. When the negation is applied to the source of an instruction that
   cannot have source modifiers.  This includes texture instructions and
   math box instructions on pre-Gen7 platforms (see more details below).

In many these cases the negation can be propagated into the instructions
that generate the value (e.g., -(a*b) = (-a)*b).

In addition to the operations implemtned in this patch, I also tried:

 - frcp - Helped 6 or fewer shaders on Gen7+, and hurt just as many on
   pre-Gen7.  On Gen6 and earlier, frcp is a math box instruction, and
   math box instructions cannot have source modifiers.

   I suspect this is why so many more shaders are helped on Gen6 than on
   Gen5 or Gen7.  Gen6 supports OpenGL 3.3, so a lot more shaders
   compile on it.  A lot of these shaders may have things like cos(-x)
   or rcp(-x) that could result in an explicit negation instruction.

 - bcsel - Hurt a few shaders with none helped.  bcsel operates on
   integer sources, so the fabs or fneg cannot be a source modifier in
   the bcsel itself.

 - Integer instructions - No changes on any Intel platform.

Some notes about the shader-db results below.

 - On Tiger Lake, a single Deus Ex fragment shader is hurt for both
   spills and fills.

 - On Haswell, a different Deus Ex fragment shader is hurt for both
   spills and fills.

 - On GM45, the "LOST: 1" and "GAINED: 1" is a single Left4Dead 2
   (very high graphics settings, lol) fragment shader that upgrades
   from SIMD8 to SIMD16.

v2: Add support for fsign.  Add some patterns that remove redundant
negations and redundant absolute value rather than trying to push them
down the tree.

Tiger Lake
total instructions in shared programs: 17611333 -> 17586465 (-0.14%)
instructions in affected programs: 3033734 -> 3008866 (-0.82%)
helped: 10310
HURT: 632
helped stats (abs) min: 1 max: 35 x̄: 2.61 x̃: 1
helped stats (rel) min: 0.04% max: 16.67% x̄: 1.43% x̃: 1.01%
HURT stats (abs)   min: 1 max: 47 x̄: 3.21 x̃: 2
HURT stats (rel)   min: 0.04% max: 5.08% x̄: 0.88% x̃: 0.63%
95% mean confidence interval for instructions value: -2.33 -2.21
95% mean confidence interval for instructions %-change: -1.32% -1.27%
Instructions are helped.

total cycles in shared programs: 338365223 -> 338262252 (-0.03%)
cycles in affected programs: 125291811 -> 125188840 (-0.08%)
helped: 5224
HURT: 2031
helped stats (abs) min: 1 max: 5670 x̄: 46.73 x̃: 12
helped stats (rel) min: <.01% max: 34.78% x̄: 1.91% x̃: 0.97%
HURT stats (abs)   min: 1 max: 2882 x̄: 69.50 x̃: 14
HURT stats (rel)   min: <.01% max: 44.93% x̄: 2.35% x̃: 0.74%
95% mean confidence interval for cycles value: -18.71 -9.68
95% mean confidence interval for cycles %-change: -0.80% -0.63%
Cycles are helped.

total spills in shared programs: 8942 -> 8946 (0.04%)
spills in affected programs: 8 -> 12 (50.00%)
helped: 0
HURT: 1

total fills in shared programs: 9399 -> 9401 (0.02%)
fills in affected programs: 21 -> 23 (9.52%)
helped: 0
HURT: 1

Ice Lake
total instructions in shared programs: 16124348 -> 16102258 (-0.14%)
instructions in affected programs: 2830928 -> 2808838 (-0.78%)
helped: 11294
HURT: 2
helped stats (abs) min: 1 max: 12 x̄: 1.96 x̃: 1
helped stats (rel) min: 0.07% max: 17.65% x̄: 1.32% x̃: 0.93%
HURT stats (abs)   min: 1 max: 1 x̄: 1.00 x̃: 1
HURT stats (rel)   min: 3.45% max: 4.00% x̄: 3.72% x̃: 3.72%
95% mean confidence interval for instructions value: -1.99 -1.93
95% mean confidence interval for instructions %-change: -1.34% -1.29%
Instructions are helped.

total cycles in shared programs: 335393932 -> 335325794 (-0.02%)
cycles in affected programs: 123834609 -> 123766471 (-0.06%)
helped: 5034
HURT: 2128
helped stats (abs) min: 1 max: 3256 x̄: 43.39 x̃: 11
helped stats (rel) min: <.01% max: 35.79% x̄: 1.98% x̃: 1.00%
HURT stats (abs)   min: 1 max: 2634 x̄: 70.63 x̃: 16
HURT stats (rel)   min: <.01% max: 49.49% x̄: 2.73% x̃: 0.62%
95% mean confidence interval for cycles value: -13.66 -5.37
95% mean confidence interval for cycles %-change: -0.69% -0.48%
Cycles are helped.

LOST:   0
GAINED: 2

Skylake
total instructions in shared programs: 14949240 -> 14927930 (-0.14%)
instructions in affected programs: 2594756 -> 2573446 (-0.82%)
helped: 11000
HURT: 2
helped stats (abs) min: 1 max: 12 x̄: 1.94 x̃: 1
helped stats (rel) min: 0.07% max: 18.75% x̄: 1.39% x̃: 0.94%
HURT stats (abs)   min: 1 max: 1 x̄: 1.00 x̃: 1
HURT stats (rel)   min: 4.76% max: 4.76% x̄: 4.76% x̃: 4.76%
95% mean confidence interval for instructions value: -1.97 -1.91
95% mean confidence interval for instructions %-change: -1.42% -1.37%
Instructions are helped.

total cycles in shared programs: 324829346 -> 324821596 (<.01%)
cycles in affected programs: 121566087 -> 121558337 (<.01%)
helped: 4611
HURT: 2147
helped stats (abs) min: 1 max: 3715 x̄: 33.29 x̃: 10
helped stats (rel) min: <.01% max: 36.08% x̄: 1.94% x̃: 1.00%
HURT stats (abs)   min: 1 max: 2551 x̄: 67.88 x̃: 16
HURT stats (rel)   min: <.01% max: 53.79% x̄: 3.69% x̃: 0.89%
95% mean confidence interval for cycles value: -4.25 1.96
95% mean confidence interval for cycles %-change: -0.28% -0.02%
Inconclusive result (value mean confidence interval includes 0).

Broadwell
total instructions in shared programs: 14971203 -> 14949957 (-0.14%)
instructions in affected programs: 2635699 -> 2614453 (-0.81%)
helped: 10982
HURT: 2
helped stats (abs) min: 1 max: 12 x̄: 1.93 x̃: 1
helped stats (rel) min: 0.07% max: 18.75% x̄: 1.39% x̃: 0.94%
HURT stats (abs)   min: 1 max: 1 x̄: 1.00 x̃: 1
HURT stats (rel)   min: 4.76% max: 4.76% x̄: 4.76% x̃: 4.76%
95% mean confidence interval for instructions value: -1.97 -1.90
95% mean confidence interval for instructions %-change: -1.42% -1.37%
Instructions are helped.

total cycles in shared programs: 336215033 -> 336086458 (-0.04%)
cycles in affected programs: 127383198 -> 127254623 (-0.10%)
helped: 4884
HURT: 1963
helped stats (abs) min: 1 max: 25696 x̄: 51.78 x̃: 12
helped stats (rel) min: <.01% max: 58.28% x̄: 2.00% x̃: 1.05%
HURT stats (abs)   min: 1 max: 3401 x̄: 63.33 x̃: 16
HURT stats (rel)   min: <.01% max: 39.95% x̄: 2.20% x̃: 0.70%
95% mean confidence interval for cycles value: -29.99 -7.57
95% mean confidence interval for cycles %-change: -0.89% -0.71%
Cycles are helped.

total fills in shared programs: 24905 -> 24901 (-0.02%)
fills in affected programs: 117 -> 113 (-3.42%)
helped: 4
HURT: 0

LOST:   0
GAINED: 16

Haswell
total instructions in shared programs: 13148927 -> 13131528 (-0.13%)
instructions in affected programs: 2220941 -> 2203542 (-0.78%)
helped: 8017
HURT: 4
helped stats (abs) min: 1 max: 12 x̄: 2.17 x̃: 1
helped stats (rel) min: 0.07% max: 15.25% x̄: 1.40% x̃: 0.93%
HURT stats (abs)   min: 1 max: 7 x̄: 2.50 x̃: 1
HURT stats (rel)   min: 0.33% max: 4.76% x̄: 2.73% x̃: 2.91%
95% mean confidence interval for instructions value: -2.21 -2.13
95% mean confidence interval for instructions %-change: -1.43% -1.37%
Instructions are helped.

total cycles in shared programs: 321221791 -> 321079870 (-0.04%)
cycles in affected programs: 126886055 -> 126744134 (-0.11%)
helped: 4674
HURT: 1729
helped stats (abs) min: 1 max: 23654 x̄: 56.47 x̃: 16
helped stats (rel) min: <.01% max: 53.22% x̄: 2.13% x̃: 1.05%
HURT stats (abs)   min: 1 max: 3694 x̄: 70.58 x̃: 18
HURT stats (rel)   min: <.01% max: 63.06% x̄: 2.48% x̃: 0.90%
95% mean confidence interval for cycles value: -33.31 -11.02
95% mean confidence interval for cycles %-change: -0.99% -0.78%
Cycles are helped.

total spills in shared programs: 19872 -> 19874 (0.01%)
spills in affected programs: 21 -> 23 (9.52%)
helped: 0
HURT: 1

total fills in shared programs: 20941 -> 20941 (0.00%)
fills in affected programs: 62 -> 62 (0.00%)
helped: 1
HURT: 1

LOST:   0
GAINED: 8

Ivy Bridge
total instructions in shared programs: 11875553 -> 11853839 (-0.18%)
instructions in affected programs: 1553112 -> 1531398 (-1.40%)
helped: 7304
HURT: 3
helped stats (abs) min: 1 max: 16 x̄: 2.97 x̃: 2
helped stats (rel) min: 0.07% max: 15.25% x̄: 1.62% x̃: 1.15%
HURT stats (abs)   min: 1 max: 1 x̄: 1.00 x̃: 1
HURT stats (rel)   min: 1.05% max: 3.33% x̄: 2.44% x̃: 2.94%
95% mean confidence interval for instructions value: -3.04 -2.90
95% mean confidence interval for instructions %-change: -1.65% -1.59%
Instructions are helped.

total cycles in shared programs: 178246425 -> 178184484 (-0.03%)
cycles in affected programs: 13702146 -> 13640205 (-0.45%)
helped: 4409
HURT: 1566
helped stats (abs) min: 1 max: 531 x̄: 24.52 x̃: 13
helped stats (rel) min: <.01% max: 38.67% x̄: 2.14% x̃: 1.02%
HURT stats (abs)   min: 1 max: 356 x̄: 29.48 x̃: 10
HURT stats (rel)   min: <.01% max: 64.73% x̄: 1.87% x̃: 0.70%
95% mean confidence interval for cycles value: -11.60 -9.14
95% mean confidence interval for cycles %-change: -1.19% -0.99%
Cycles are helped.

LOST:   0
GAINED: 10

Sandy Bridge
total instructions in shared programs: 10695740 -> 10667483 (-0.26%)
instructions in affected programs: 2337607 -> 2309350 (-1.21%)
helped: 10720
HURT: 1
helped stats (abs) min: 1 max: 49 x̄: 2.64 x̃: 2
helped stats (rel) min: 0.07% max: 20.00% x̄: 1.54% x̃: 1.13%
HURT stats (abs)   min: 1 max: 1 x̄: 1.00 x̃: 1
HURT stats (rel)   min: 1.04% max: 1.04% x̄: 1.04% x̃: 1.04%
95% mean confidence interval for instructions value: -2.69 -2.58
95% mean confidence interval for instructions %-change: -1.57% -1.51%
Instructions are helped.

total cycles in shared programs: 153478839 -> 153416223 (-0.04%)
cycles in affected programs: 22050900 -> 21988284 (-0.28%)
helped: 5342
HURT: 2200
helped stats (abs) min: 1 max: 1020 x̄: 20.34 x̃: 16
helped stats (rel) min: <.01% max: 24.05% x̄: 1.51% x̃: 0.86%
HURT stats (abs)   min: 1 max: 335 x̄: 20.93 x̃: 6
HURT stats (rel)   min: <.01% max: 20.18% x̄: 1.03% x̃: 0.30%
95% mean confidence interval for cycles value: -9.18 -7.42
95% mean confidence interval for cycles %-change: -0.82% -0.71%
Cycles are helped.

Iron Lake
total instructions in shared programs: 8114882 -> 8105574 (-0.11%)
instructions in affected programs: 1232504 -> 1223196 (-0.76%)
helped: 4109
HURT: 2
helped stats (abs) min: 1 max: 6 x̄: 2.27 x̃: 1
helped stats (rel) min: 0.05% max: 8.33% x̄: 0.99% x̃: 0.66%
HURT stats (abs)   min: 1 max: 1 x̄: 1.00 x̃: 1
HURT stats (rel)   min: 0.94% max: 4.35% x̄: 2.65% x̃: 2.65%
95% mean confidence interval for instructions value: -2.31 -2.21
95% mean confidence interval for instructions %-change: -1.01% -0.96%
Instructions are helped.

total cycles in shared programs: 188504036 -> 188466296 (-0.02%)
cycles in affected programs: 31203798 -> 31166058 (-0.12%)
helped: 3447
HURT: 36
helped stats (abs) min: 2 max: 92 x̄: 11.03 x̃: 8
helped stats (rel) min: <.01% max: 5.41% x̄: 0.21% x̃: 0.13%
HURT stats (abs)   min: 2 max: 30 x̄: 7.33 x̃: 6
HURT stats (rel)   min: 0.01% max: 1.65% x̄: 0.18% x̃: 0.10%
95% mean confidence interval for cycles value: -11.16 -10.51
95% mean confidence interval for cycles %-change: -0.22% -0.20%
Cycles are helped.

LOST:   0
GAINED: 1

GM45
total instructions in shared programs: 4989697 -> 4984531 (-0.10%)
instructions in affected programs: 703952 -> 698786 (-0.73%)
helped: 2493
HURT: 2
helped stats (abs) min: 1 max: 6 x̄: 2.07 x̃: 1
helped stats (rel) min: 0.05% max: 8.33% x̄: 1.03% x̃: 0.66%
HURT stats (abs)   min: 1 max: 1 x̄: 1.00 x̃: 1
HURT stats (rel)   min: 0.95% max: 4.35% x̄: 2.65% x̃: 2.65%
95% mean confidence interval for instructions value: -2.13 -2.01
95% mean confidence interval for instructions %-change: -1.07% -0.99%
Instructions are helped.

total cycles in shared programs: 128929136 -> 128903886 (-0.02%)
cycles in affected programs: 21583096 -> 21557846 (-0.12%)
helped: 2214
HURT: 17
helped stats (abs) min: 2 max: 92 x̄: 11.44 x̃: 8
helped stats (rel) min: <.01% max: 5.41% x̄: 0.24% x̃: 0.13%
HURT stats (abs)   min: 2 max: 8 x̄: 4.24 x̃: 4
HURT stats (rel)   min: 0.01% max: 1.65% x̄: 0.20% x̃: 0.09%
95% mean confidence interval for cycles value: -11.75 -10.88
95% mean confidence interval for cycles %-change: -0.25% -0.22%
Cycles are helped.

LOST:   1
GAINED: 1

Reviewed-by: Matt Turner <mattst88@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/1359>
2020-04-01 00:28:38 +00:00
..
brw_cfg.cpp intel/compiler: Pass backend_shader * to cfg_t() 2020-03-09 04:44:12 +00:00
brw_cfg.h intel/compiler: Pass backend_shader * to cfg_t() 2020-03-09 04:44:12 +00:00
brw_clip.h
brw_clip_line.c
brw_clip_point.c
brw_clip_tri.c i965: Don't emit MOVs with undefined registers for Gen4 point clipping. 2018-02-28 15:03:51 -08:00
brw_clip_unfilled.c
brw_clip_util.c
brw_compile_clip.c intel/common: move gen_debug to intel/dev 2019-04-10 13:15:33 -07:00
brw_compile_sf.c intel/common: move gen_debug to intel/dev 2019-04-10 13:15:33 -07:00
brw_compiler.c nir, intel: Move use_scoped_memory_barrier to nir_options 2020-02-24 19:12:11 +00:00
brw_compiler.h intel/compiler: Track patch count threshold 2020-03-23 17:57:57 +00:00
brw_dead_control_flow.cpp intel/compiler: Pass detailed dependency classes to invalidate_analysis() 2020-03-06 10:20:39 -08:00
brw_dead_control_flow.h
brw_debug_recompile.c intel/compiler: Add a "base class" for program keys 2019-07-10 19:35:55 +00:00
brw_disasm.c intel/gen12: Take into account opcode when decoding SWSB 2020-02-18 09:17:51 -08:00
brw_disasm_info.c intel/common: move gen_debug to intel/dev 2019-04-10 13:15:33 -07:00
brw_disasm_info.h
brw_eu.cpp intel/disasm: SEND has two sources on Gen12+ 2020-01-31 17:23:39 +00:00
brw_eu.h intel/compiler: Move Gen4/5 rounding to visitor 2020-01-22 23:47:02 +00:00
brw_eu_compact.c intel/compiler: Handle invalid compacted immediates 2020-01-22 00:19:21 +00:00
brw_eu_defines.h intel/gen12: Take into account opcode when decoding SWSB 2020-02-18 09:17:51 -08:00
brw_eu_emit.c intel/fs: Don't unnecessarily fall back to indirect sends on Gen12 2020-01-24 19:18:27 +00:00
brw_eu_util.c
brw_eu_validate.c intel/eu/validate: Don't validate regions of sends 2020-01-31 17:23:39 +00:00
brw_fs.cpp intel/fs: Fix NULL destinations on 3-source instructions again after late DCE 2020-03-12 08:22:43 -07:00
brw_fs.h i965: Move down genX_upload_sbe in profiles. 2020-03-10 14:28:36 +00:00
brw_fs_bank_conflicts.cpp intel/fs/gen6: Constrain barycentric source of LINTERP during bank conflict mitigation. 2020-01-17 13:22:29 -08:00
brw_fs_builder.h intel/fs/gen7+: Swap sample mask flag register and FIND_LIVE_CHANNEL temporary. 2020-02-14 14:31:48 -08:00
brw_fs_cmod_propagation.cpp intel/compiler: fix cmod propagation optimisations 2020-03-11 21:21:25 +00:00
brw_fs_combine_constants.cpp intel/compiler: Move idom tree calculation and related logic into analysis object 2020-03-06 10:21:03 -08:00
brw_fs_copy_propagation.cpp intel/compiler/fs: Switch liveness analysis to IR analysis framework 2020-03-06 10:20:57 -08:00
brw_fs_cse.cpp intel/compiler/fs: Switch liveness analysis to IR analysis framework 2020-03-06 10:20:57 -08:00
brw_fs_dead_code_eliminate.cpp intel/compiler/fs: Switch liveness analysis to IR analysis framework 2020-03-06 10:20:57 -08:00
brw_fs_generator.cpp intel/fs: Fix workaround for VxH indirect addressing bug under control flow. 2020-03-10 00:42:50 +00:00
brw_fs_live_variables.cpp intel/compiler: Drop invalidate_live_intervals() 2020-03-06 10:21:01 -08:00
brw_fs_live_variables.h intel/compiler/fs: Switch liveness analysis to IR analysis framework 2020-03-06 10:20:57 -08:00
brw_fs_lower_pack.cpp intel/compiler: Pass detailed dependency classes to invalidate_analysis() 2020-03-06 10:20:39 -08:00
brw_fs_lower_regioning.cpp intel/compiler: Pass detailed dependency classes to invalidate_analysis() 2020-03-06 10:20:39 -08:00
brw_fs_nir.cpp intel/fs: Allow NOT instructions in conditional discard optimization 2020-03-09 16:46:28 -07:00
brw_fs_reg_allocate.cpp intel/compiler: Mark some methods and parameters const 2020-03-09 04:44:11 +00:00
brw_fs_register_coalesce.cpp intel/compiler/fs: Switch liveness analysis to IR analysis framework 2020-03-06 10:20:57 -08:00
brw_fs_saturate_propagation.cpp intel/compiler/fs: Switch liveness analysis to IR analysis framework 2020-03-06 10:20:57 -08:00
brw_fs_scoreboard.cpp intel/fs/gen12: Fix interaction of SWSB dependency combination with EU fusion workaround. 2020-03-26 19:09:42 +00:00
brw_fs_sel_peephole.cpp intel/compiler: Pass detailed dependency classes to invalidate_analysis() 2020-03-06 10:20:39 -08:00
brw_fs_validate.cpp intel: disable FS IR validation in release mode. 2018-10-15 18:10:27 -07:00
brw_fs_visitor.cpp i965: Move down genX_upload_sbe in profiles. 2020-03-10 14:28:36 +00:00
brw_gen_enum.h intel/compiler: Extract GEN_* macros into separate file 2020-01-22 00:19:20 +00:00
brw_inst.h intel/compiler: Fix array bounds warning on GCC 10. 2020-01-22 08:35:18 +01:00
brw_interpolation_map.c intel/compiler: Silence unused parameter warning in brw_interpolation_map.c 2019-03-06 08:35:36 -08:00
brw_ir.h intel/compiler: Move base IR definitions into a separate header file 2020-03-06 10:20:11 -08:00
brw_ir_allocator.h intel/ir: Don't allow allocating zero registers 2018-12-11 21:26:23 -06:00
brw_ir_analysis.h intel/compiler: Define more detailed analysis dependency classes 2020-03-06 10:20:37 -08:00
brw_ir_fs.h intel/fs: Rework fs_inst::is_copy_payload() into multiple classification helpers. 2020-01-17 13:21:19 -08:00
brw_ir_vec4.h intel/compiler: Mark some methods and parameters const 2020-03-09 04:44:11 +00:00
brw_nir.c nir/algebraic: Distribute source modifiers into instructions 2020-04-01 00:28:38 +00:00
brw_nir.h intel/compiler: detect if atomic load store operations are used 2020-03-16 10:34:21 +00:00
brw_nir_analyze_boolean_resolves.c intel/fs: Mark source 0 of bcsel as needing Boolean resolve 2019-06-11 12:12:07 -07:00
brw_nir_analyze_ubo_ranges.c intel/compiler: Do not qsort zero sized array 2020-02-19 12:07:24 +02:00
brw_nir_attribute_workarounds.c nir/builder: Remove the use_fmov parameter from nir_swizzle 2019-05-24 08:38:11 -05:00
brw_nir_clamp_image_1d_2d_array_sizes.c intel: Implement Gen12 workaround for array textures of size 1 2020-01-26 22:27:03 +02:00
brw_nir_lower_alpha_to_coverage.c nir: Add alpha_to_coverage lowering pass 2019-10-21 11:27:29 -07:00
brw_nir_lower_conversions.c intel/compiler: add a NIR pass to lower conversions 2019-04-18 11:05:18 +02:00
brw_nir_lower_cs_intrinsics.c intel/nir: Stop adding redundant barriers 2020-01-13 17:23:47 +00:00
brw_nir_lower_image_load_store.c intel/compiler: detect if atomic load store operations are used 2020-03-16 10:34:21 +00:00
brw_nir_lower_mem_access_bit_sizes.c intel/fs: Implement the new load/store_scratch intrinsics 2019-11-11 17:17:02 +00:00
brw_nir_opt_peephole_ffma.c util: rename list_empty() to list_is_empty() 2019-10-28 11:24:38 +00:00
brw_nir_tcs_workarounds.c util: use C99 declaration in the for-loop set_foreach() macro 2018-10-25 12:43:18 +01:00
brw_nir_trig_workarounds.py intel/nir: do not apply the fsin and fcos trig workarounds for consts 2019-09-17 23:39:18 +03:00
brw_packed_float.c intel/compiler: Cast to target type before shifting left 2019-10-24 16:19:23 +02:00
brw_predicated_break.cpp intel/compiler: Pass detailed dependency classes to invalidate_analysis() 2020-03-06 10:20:39 -08:00
brw_reg.h Move compiler.h and imports.h/c from src/mesa/main into src/util 2020-03-27 21:00:09 +00:00
brw_reg_type.c intel/compiler: Handle invalid inputs to brw_reg_type_to_*() 2020-01-22 00:19:21 +00:00
brw_reg_type.h intel/compiler: Add a INVALID_{,HW_}REG_TYPE macros 2020-01-22 00:19:20 +00:00
brw_schedule_instructions.cpp intel/compiler: Mark visitor parameters to scheduler const 2020-03-09 04:44:12 +00:00
brw_shader.cpp intel/compiler: Pass shader_stats for each SIMD mode 2020-03-09 04:44:12 +00:00
brw_shader.h intel/compiler: Mark some methods and parameters const 2020-03-09 04:44:11 +00:00
brw_vec4.cpp intel/compiler: Pass shader_stats for each SIMD mode 2020-03-09 04:44:12 +00:00
brw_vec4.h intel/compiler: Mark some methods and parameters const 2020-03-09 04:44:11 +00:00
brw_vec4_builder.h intel/compiler: Lower flrp32 on Gen11+ 2018-02-28 11:15:47 -08:00
brw_vec4_cmod_propagation.cpp intel/compiler: Pass detailed dependency classes to invalidate_analysis() 2020-03-06 10:20:39 -08:00
brw_vec4_copy_propagation.cpp intel/compiler: Pass detailed dependency classes to invalidate_analysis() 2020-03-06 10:20:39 -08:00
brw_vec4_cse.cpp intel/compiler/vec4: Switch liveness analysis to IR analysis framework 2020-03-06 10:20:59 -08:00
brw_vec4_dead_code_eliminate.cpp intel/compiler/vec4: Switch liveness analysis to IR analysis framework 2020-03-06 10:20:59 -08:00
brw_vec4_generator.cpp intel/compiler: Report the number of non-spill/fill SEND messages on vec4 too 2019-10-30 21:27:03 -07:00
brw_vec4_gs_nir.cpp intel/vec4: Drop all of the 64-bit varying code 2019-07-31 18:14:09 -05:00
brw_vec4_gs_visitor.cpp intel/compiler: Pass shader_stats for each SIMD mode 2020-03-09 04:44:12 +00:00
brw_vec4_gs_visitor.h
brw_vec4_live_variables.cpp intel/compiler: Drop invalidate_live_intervals() 2020-03-06 10:21:01 -08:00
brw_vec4_live_variables.h intel/compiler/vec4: Switch liveness analysis to IR analysis framework 2020-03-06 10:20:59 -08:00
brw_vec4_nir.cpp intel/vec4: fix valgrind errors with vf_values array 2020-02-07 09:06:18 +00:00
brw_vec4_reg_allocate.cpp intel/compiler/vec4: Switch liveness analysis to IR analysis framework 2020-03-06 10:20:59 -08:00
brw_vec4_surface_builder.cpp intel/compiler: Re-prefix non-logical surface opcodes with VEC4 2019-02-28 16:58:20 -06:00
brw_vec4_surface_builder.h intel/vec4: Drop dead code for handling typed surface messages 2019-02-28 16:58:20 -06:00
brw_vec4_tcs.cpp intel/compiler: Track patch count threshold 2020-03-23 17:57:57 +00:00
brw_vec4_tcs.h
brw_vec4_tes.cpp intel/vec4: Drop all of the 64-bit varying code 2019-07-31 18:14:09 -05:00
brw_vec4_tes.h
brw_vec4_visitor.cpp intel/compiler/vec4: Switch liveness analysis to IR analysis framework 2020-03-06 10:20:59 -08:00
brw_vec4_vs.h i965: Use NIR to lower legacy userclipping. 2019-07-24 18:00:13 +00:00
brw_vec4_vs_visitor.cpp i965: Use NIR to lower legacy userclipping. 2019-07-24 18:00:13 +00:00
brw_vue_map.c intel/compiler: silence a warning of using different enum type 2019-06-25 10:09:22 +03:00
brw_wm_iz.cpp intel: Use a system value for gl_FragCoord 2019-07-29 23:30:26 +00:00
gen6_gs_visitor.cpp intel/compiler: Prevent warnings in the following patch 2019-01-09 16:42:41 -08:00
gen6_gs_visitor.h
meson.build intel: drop unused include directories 2020-03-28 21:36:54 +01:00
test_eu_compact.cpp intel/compiler: Test compaction on Gen <= 12 2020-01-22 00:19:21 +00:00
test_eu_validate.cpp util: Remove tmp argument from BITSET_FOREACH_SET macro 2020-01-23 01:52:43 +00:00
test_fs_cmod_propagation.cpp intel/compiler: fix cmod propagation optimisations 2020-03-11 21:21:25 +00:00
test_fs_copy_propagation.cpp intel/compiler: Pass backend_shader * to cfg_t() 2020-03-09 04:44:12 +00:00
test_fs_saturate_propagation.cpp intel/compiler: Pass backend_shader * to cfg_t() 2020-03-09 04:44:12 +00:00
test_fs_scoreboard.cpp intel/compiler: Pass backend_shader * to cfg_t() 2020-03-09 04:44:12 +00:00
test_vec4_cmod_propagation.cpp i965/vec4: Silence unused parameter warnings in vec4 compiler tests 2018-12-17 13:47:06 -08:00
test_vec4_copy_propagation.cpp i965/vec4: Silence unused parameter warnings in vec4 compiler tests 2018-12-17 13:47:06 -08:00
test_vec4_dead_code_eliminate.cpp i965/vec4/dce: Don't narrow the write mask if the flags are used 2018-12-17 13:47:06 -08:00
test_vec4_register_coalesce.cpp i965/vec4: Silence unused parameter warnings in vec4 compiler tests 2018-12-17 13:47:06 -08:00
test_vf_float_conversions.cpp