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622c2498d4
This implements a minimalistic algorithm that can be used to obtain an approximate solution for the integer programming problem of finding the optimal tile dimensions based on an estimate of the tile cache consumption per pixel of the current graphics pipeline -- Including the TC footprint of render targets, depth and stencil buffers and their auxiliary surfaces. Considering other (less local) memory accesses performed by the pipeline (like texturing and shader storage) would be useful (and could be considered by this algorithm with little modification), but it would be pretty difficult to estimate the L3 cache consumption per pixel of such accesses based on static analysis of the pipeline state alone without some sort of dynamic feedback. The present algorithm returns a config with tile area large enough to utilize a target fraction of the L3, which can be adjusted to obtain greater/lower utilization of the L3 at the cost of higher/lower risk of L3 cache thrashing respectively. The aspect ratio of the tile layout returned attempts to minimize the number of poorly utilized tiles around the boundaries of the framebuffer (due to partial coverage), since having the tile sequencer process additional tiles comes at a cost due to the latency of the additional passes, even if they're mostly empty. Finally, among the solutions with satisfactory cache footprint and tile count, the tile aspect ratio closest to 1 is returned where possible, since tiles with very high aspect ratios can have a negative impact on cache locality. The algorithm is primarily intended for TBIMR, but it could be used for PTBR as well with little modifications, since the TBIMR-specific assumptions are few and noted in comments below. Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25493> |
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