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c2ac7fa77b
No shader-db chnages on any Intel platform. v2: Add a note about integer types in the saturate handling path. fossil-db: All Intel platforms had similar results. (Lunar Lake shown) Totals: Instrs: 210743769 -> 210743727 (-0.00%) Cycle count: 30377699060 -> 30377700318 (+0.00%); split: -0.00%, +0.00% Totals from 36 (0.01% of 706776) affected shaders: Instrs: 17032 -> 16990 (-0.25%) Cycle count: 291716 -> 292974 (+0.43%); split: -0.01%, +0.44% Reviewed-by: Matt Turner <mattst88@gmail.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/34509>
563 lines
23 KiB
C++
563 lines
23 KiB
C++
/*
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* Copyright © 2014 Intel Corporation
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice (including the next
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* paragraph) shall be included in all copies or substantial portions of the
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* Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
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* IN THE SOFTWARE.
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*/
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#include "brw_shader.h"
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#include "brw_cfg.h"
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#include "brw_eu.h"
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#include "util/half_float.h"
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/** @file
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*
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* Implements a pass that propagates the conditional modifier from a CMP x 0.0
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* instruction into the instruction that generated x. For instance, in this
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* sequence
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*
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* add(8) g70<1>F g69<8,8,1>F 4096F
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* cmp.ge.f0(8) null g70<8,8,1>F 0F
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*
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* we can do the comparison as part of the ADD instruction directly:
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*
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* add.ge.f0(8) g70<1>F g69<8,8,1>F 4096F
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*
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* If there had been a use of the flag register and another CMP using g70
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*
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* add.ge.f0(8) g70<1>F g69<8,8,1>F 4096F
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* (+f0) sel(8) g71<F> g72<8,8,1>F g73<8,8,1>F
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* cmp.ge.f0(8) null g70<8,8,1>F 0F
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*
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* we can recognize that the CMP is generating the flag value that already
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* exists and therefore remove the instruction.
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*/
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static double
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src_as_float(const brw_reg &src)
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{
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assert(src.file == IMM);
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switch (src.type) {
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case BRW_TYPE_HF:
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return _mesa_half_to_float((uint16_t)src.d);
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case BRW_TYPE_F:
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return src.f;
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case BRW_TYPE_DF:
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return src.df;
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default:
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unreachable("Invalid float type.");
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}
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}
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static bool
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cmod_propagate_cmp_to_add(const intel_device_info *devinfo, brw_inst *inst)
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{
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bool read_flag = false;
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const unsigned flags_written = inst->flags_written(devinfo);
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/* The floating point comparison can only be removed if we can prove that
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* either the addition is not ±Inf - (±Inf) or that ±Inf - (±Inf) compared
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* with zero has the same result as ±Inf compared with ±Inf.
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*
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* The former can only be proven at this point in compilation if src[1] is
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* an immediate value. Otherwise we can't know that nether value is
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* ±Inf. For the latter, consider this table:
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*
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* A B A+(-B) A<B A-B<0 A<=B A-B<=0 A>B A-B>0 A>=B A-B>=0 A==B A-B==0 A!=B A-B!=0
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* Inf Inf NaN F F T F F F T F T F F T
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* Inf -Inf Inf F F F F T T T T F F T T
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* -Inf Inf -Inf T T T T F F F F F F T T
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* -Inf -Inf NaN F F T F F F T F T F F T
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*
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* The column for A<B and A-B<0 is identical, and the column for A>B and
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* A-B>0 are identical.
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*
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* If src[1] is NaN, the transformation is always valid.
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*/
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if (brw_type_is_float(inst->src[0].type)) {
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if (inst->conditional_mod != BRW_CONDITIONAL_L &&
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inst->conditional_mod != BRW_CONDITIONAL_G) {
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if (inst->src[1].file != IMM)
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return false;
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if (isinf(src_as_float(inst->src[1])) != 0)
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return false;
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}
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} else {
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/* This optimization can fail for integers. For inputs a = 0x80000000,
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* b = 4, int(0x80000000) < 4, but int(0x80000000) - 4 overflows and
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* results in 0x7ffffffc. that's not less than zero, so the flags get
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* set differently than for (a < b).
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*
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* However, it is safe if the comparison is Z or NZ.
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*/
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if (inst->conditional_mod != BRW_CONDITIONAL_Z &&
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inst->conditional_mod != BRW_CONDITIONAL_NZ)
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return false;
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}
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foreach_inst_in_block_reverse_starting_from(brw_inst, scan_inst, inst) {
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if (scan_inst->opcode == BRW_OPCODE_ADD &&
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!scan_inst->predicate &&
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scan_inst->dst.is_contiguous() &&
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scan_inst->exec_size == inst->exec_size) {
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bool negate;
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/* A CMP is basically a subtraction. The result of the
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* subtraction must be the same as the result of the addition.
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* This means that one of the operands must be negated. So (a +
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* b) vs (a == -b) or (a + -b) vs (a == b).
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*/
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if ((inst->src[0].equals(scan_inst->src[0]) &&
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inst->src[1].negative_equals(scan_inst->src[1])) ||
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(inst->src[0].equals(scan_inst->src[1]) &&
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inst->src[1].negative_equals(scan_inst->src[0]))) {
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negate = false;
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} else if ((inst->src[0].negative_equals(scan_inst->src[0]) &&
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inst->src[1].equals(scan_inst->src[1])) ||
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(inst->src[0].negative_equals(scan_inst->src[1]) &&
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inst->src[1].equals(scan_inst->src[0]))) {
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negate = true;
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} else {
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goto not_match;
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}
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/* If the scan instruction writes a different flag register than the
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* instruction we're trying to propagate from, bail.
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*
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* FINISHME: The second part of the condition may be too strong.
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* Perhaps (scan_inst->flags_written() & flags_written) !=
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* flags_written?
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*/
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if (scan_inst->flags_written(devinfo) != 0 &&
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scan_inst->flags_written(devinfo) != flags_written)
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goto not_match;
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/* From the Kaby Lake PRM Vol. 7 "Assigning Conditional Flags":
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*
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* * Note that the [post condition signal] bits generated at
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* the output of a compute are before the .sat.
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*
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* Paragraph about post_zero does not mention saturation, but
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* testing it on actual GPUs shows that conditional modifiers
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* are applied after saturation.
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*
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* * post_zero bit: This bit reflects whether the final
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* result is zero after all the clamping, normalizing,
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* or format conversion logic.
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*
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* For signed types we don't care about saturation: it won't
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* change the result of conditional modifier.
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*
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* For floating and unsigned types there two special cases,
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* when we can remove inst even if scan_inst is saturated: G
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* and LE. Since conditional modifiers are just comparisons
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* against zero, saturating positive values to the upper
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* limit never changes the result of comparison.
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*
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* For negative values:
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* (sat(x) > 0) == (x > 0) --- false
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* (sat(x) <= 0) == (x <= 0) --- true
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*
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* Except for the x = NaN cases. sat(NaN) is 0, so add.sat.le of a
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* NaN result will be true. add.sat.g of a NaN result is false, so
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* the optimization is also incorrect when the second source of the
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* comparison is less than zero. All of the fsat(x) > is_negative
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* cases should have been eliminated in NIR.
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*/
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const enum brw_conditional_mod cond =
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negate ? brw_swap_cmod(inst->conditional_mod)
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: inst->conditional_mod;
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if (scan_inst->saturate) {
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/* Note: Integer types can only have NZ or Z, so this path does
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* not need to worry about integer handling.
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*/
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if (cond != BRW_CONDITIONAL_G)
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goto not_match;
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assert(!brw_type_is_int(scan_inst->dst.type));
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if (inst->src[1].file != IMM)
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goto not_match;
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double v = src_as_float(inst->src[1]);
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if (negate)
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v = -v;
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if (v < 0.0)
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goto not_match;
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}
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/* Otherwise, try propagating the conditional. */
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if (scan_inst->can_do_cmod() &&
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((!read_flag && scan_inst->conditional_mod == BRW_CONDITIONAL_NONE) ||
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scan_inst->conditional_mod == cond)) {
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scan_inst->conditional_mod = cond;
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scan_inst->flag_subreg = inst->flag_subreg;
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inst->remove();
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return true;
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}
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break;
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}
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not_match:
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if ((scan_inst->flags_written(devinfo) & flags_written) != 0)
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break;
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read_flag = read_flag ||
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(scan_inst->flags_read(devinfo) & flags_written) != 0;
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}
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return false;
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}
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static bool
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opt_cmod_propagation_local(const intel_device_info *devinfo, bblock_t *block)
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{
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bool progress = false;
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foreach_inst_in_block_reverse_safe(brw_inst, inst, block) {
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if ((inst->opcode != BRW_OPCODE_AND &&
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inst->opcode != BRW_OPCODE_CMP &&
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inst->opcode != BRW_OPCODE_MOV) ||
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inst->predicate != BRW_PREDICATE_NONE ||
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!inst->dst.is_null() ||
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(inst->src[0].file != VGRF && inst->src[0].file != ATTR &&
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inst->src[0].file != UNIFORM))
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continue;
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/* An ABS source modifier can only be handled when processing a compare
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* with a value other than zero.
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*/
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if (inst->src[0].abs &&
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(inst->opcode != BRW_OPCODE_CMP || inst->src[1].is_zero()))
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continue;
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/* Only an AND.NZ can be propagated. Propagating AND.Z would require
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* inverting the condition on the CMP. This changes both the flag value
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* and the register destination of the CMP. That result may be used
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* elsewhere, so we can't change its value on a whim.
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*/
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if (inst->opcode == BRW_OPCODE_AND &&
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!(inst->src[1].is_one() &&
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inst->conditional_mod == BRW_CONDITIONAL_NZ &&
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!inst->src[0].negate))
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continue;
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/* A CMP with a second source of zero can match with anything. A CMP
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* with a second source that is not zero can only match with an ADD
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* instruction.
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*/
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if (inst->opcode == BRW_OPCODE_CMP && !inst->src[1].is_zero()) {
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if (cmod_propagate_cmp_to_add(devinfo, inst))
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progress = true;
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continue;
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}
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bool read_flag = false;
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const unsigned flags_written = inst->flags_written(devinfo);
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foreach_inst_in_block_reverse_starting_from(brw_inst, scan_inst, inst) {
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if (regions_overlap(scan_inst->dst, scan_inst->size_written,
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inst->src[0], inst->size_read(devinfo, 0))) {
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/* If the scan instruction writes a different flag register than
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* the instruction we're trying to propagate from, bail.
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*
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* FINISHME: The second part of the condition may be too strong.
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* Perhaps (scan_inst->flags_written() & flags_written) !=
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* flags_written?
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*/
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if (scan_inst->flags_written(devinfo) != 0 &&
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scan_inst->flags_written(devinfo) != flags_written)
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break;
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if (scan_inst->predicate ||
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!scan_inst->dst.is_contiguous() ||
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scan_inst->dst.offset != inst->src[0].offset ||
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scan_inst->exec_size != inst->exec_size)
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break;
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/* If the write mask is different we can't propagate. */
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if (scan_inst->force_writemask_all != inst->force_writemask_all)
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break;
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/* CMP's result is the same regardless of dest type. */
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if (inst->conditional_mod == BRW_CONDITIONAL_NZ &&
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scan_inst->opcode == BRW_OPCODE_CMP &&
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brw_type_is_int(inst->dst.type)) {
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inst->remove();
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progress = true;
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break;
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}
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/* If the AND wasn't handled by the previous case, it isn't safe
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* to remove it.
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*/
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if (inst->opcode == BRW_OPCODE_AND)
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break;
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if (inst->opcode == BRW_OPCODE_MOV) {
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if (brw_type_is_float(scan_inst->dst.type)) {
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/* If the destination type of scan_inst is floating-point,
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* then:
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*
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* - The source of the MOV instruction must be the same
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* type.
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*
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* - The destination of the MOV instruction must be float
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* point with a size at least as large as the destination
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* of inst. Size-reducing f2f conversions could cause
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* non-zero values to become zero, etc.
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*/
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if (scan_inst->dst.type != inst->src[0].type)
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break;
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if (!brw_type_is_float(inst->dst.type))
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break;
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if (brw_type_size_bits(scan_inst->dst.type) >
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brw_type_size_bits(inst->dst.type))
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break;
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} else {
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/* If the destination type of scan_inst is integer, then:
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*
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* - The source of the MOV instruction must be integer with
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* the same size.
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*
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* - If the conditional modifier is neither Z nor NZ, then
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* the source of the MOV instruction has to have same
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* signedness.
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*
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* - If the conditional modifier is Z or NZ, then the
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* destination type of inst must either be floating point
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* (of any size) or integer with a size at least as large
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* as the destination of inst.
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*
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* - If the conditional modifier is neither Z nor NZ, then the
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* destination type of inst must either be floating point
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* (of any size) or integer with a size at least as large
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* as the destination of inst and the same signedness.
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*/
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if (!brw_type_is_int(inst->src[0].type) ||
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brw_type_size_bits(scan_inst->dst.type) != brw_type_size_bits(inst->src[0].type))
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break;
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if (inst->conditional_mod != BRW_CONDITIONAL_Z &&
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inst->conditional_mod != BRW_CONDITIONAL_NZ &&
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brw_type_is_uint(inst->src[0].type) !=
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brw_type_is_uint(scan_inst->dst.type))
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break;
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if (brw_type_is_int(inst->dst.type)) {
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if (brw_type_size_bits(inst->dst.type) <
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brw_type_size_bits(scan_inst->dst.type))
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break;
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if (inst->conditional_mod != BRW_CONDITIONAL_Z &&
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inst->conditional_mod != BRW_CONDITIONAL_NZ &&
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brw_type_is_uint(inst->dst.type) !=
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brw_type_is_uint(scan_inst->dst.type))
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break;
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}
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}
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} else {
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/* Not safe to use inequality operators if the types are
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* different.
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*/
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if (scan_inst->dst.type != inst->src[0].type &&
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inst->conditional_mod != BRW_CONDITIONAL_Z &&
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inst->conditional_mod != BRW_CONDITIONAL_NZ)
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break;
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/* Comparisons operate differently for ints and floats */
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if (scan_inst->dst.type != inst->dst.type) {
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/* Comparison result may be altered if the bit-size changes
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* since that affects range, denorms, etc
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*/
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if (brw_type_size_bits(scan_inst->dst.type) !=
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brw_type_size_bits(inst->dst.type))
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break;
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if (brw_type_is_float(scan_inst->dst.type) !=
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brw_type_is_float(inst->dst.type))
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break;
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}
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}
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/* Knowing following:
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* - CMP writes to flag register the result of
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* applying cmod to the `src0 - src1`.
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* After that it stores the same value to dst.
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* Other instructions first store their result to
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* dst, and then store cmod(dst) to the flag
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* register.
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* - inst is either CMP or MOV
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* - inst->dst is null
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* - inst->src[0] overlaps with scan_inst->dst
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* - inst->src[1] is zero
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* - scan_inst wrote to a flag register
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*
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* There can be three possible paths:
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*
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* - scan_inst is CMP:
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*
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* Considering that src0 is either 0x0 (false),
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* or 0xffffffff (true), and src1 is 0x0:
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*
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* - If inst's cmod is NZ, we can always remove
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* scan_inst: NZ is invariant for false and true. This
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* holds even if src0 is NaN: .nz is the only cmod,
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* that returns true for NaN.
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*
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* - .g is invariant if src0 has a UD type
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*
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* - .l is invariant if src0 has a D type
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*
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* - scan_inst and inst have the same cmod:
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*
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* If scan_inst is anything than CMP, it already
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* wrote the appropriate value to the flag register.
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*
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* - else:
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*
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* We can change cmod of scan_inst to that of inst,
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* and remove inst. It is valid as long as we make
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* sure that no instruction uses the flag register
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* between scan_inst and inst.
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*/
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if (!inst->src[0].negate &&
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scan_inst->flags_written(devinfo)) {
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if (scan_inst->opcode == BRW_OPCODE_CMP) {
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if ((inst->conditional_mod == BRW_CONDITIONAL_NZ) ||
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(inst->conditional_mod == BRW_CONDITIONAL_G &&
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inst->src[0].type == BRW_TYPE_UD) ||
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(inst->conditional_mod == BRW_CONDITIONAL_L &&
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inst->src[0].type == BRW_TYPE_D)) {
|
|
inst->remove();
|
|
progress = true;
|
|
break;
|
|
}
|
|
} else if (scan_inst->conditional_mod == inst->conditional_mod) {
|
|
/* sel.cond will not write the flags. */
|
|
assert(scan_inst->opcode != BRW_OPCODE_SEL);
|
|
inst->remove();
|
|
progress = true;
|
|
break;
|
|
} else if (!read_flag && scan_inst->can_do_cmod()) {
|
|
scan_inst->conditional_mod = inst->conditional_mod;
|
|
scan_inst->flag_subreg = inst->flag_subreg;
|
|
inst->remove();
|
|
progress = true;
|
|
break;
|
|
}
|
|
}
|
|
|
|
/* The conditional mod of the CMP/CMPN instructions behaves
|
|
* specially because the flag output is not calculated from the
|
|
* result of the instruction, but the other way around, which
|
|
* means that even if the condmod to propagate and the condmod
|
|
* from the CMP instruction are the same they will in general give
|
|
* different results because they are evaluated based on different
|
|
* inputs.
|
|
*/
|
|
if (scan_inst->opcode == BRW_OPCODE_CMP ||
|
|
scan_inst->opcode == BRW_OPCODE_CMPN)
|
|
break;
|
|
|
|
/* From the Sky Lake PRM, Vol 2a, "Multiply":
|
|
*
|
|
* "When multiplying integer data types, if one of the sources
|
|
* is a DW, the resulting full precision data is stored in
|
|
* the accumulator. However, if the destination data type is
|
|
* either W or DW, the low bits of the result are written to
|
|
* the destination register and the remaining high bits are
|
|
* discarded. This results in undefined Overflow and Sign
|
|
* flags. Therefore, conditional modifiers and saturation
|
|
* (.sat) cannot be used in this case."
|
|
*
|
|
* We just disallow cmod propagation on all integer multiplies.
|
|
*/
|
|
if (!brw_type_is_float(scan_inst->dst.type) &&
|
|
scan_inst->opcode == BRW_OPCODE_MUL)
|
|
break;
|
|
|
|
enum brw_conditional_mod cond =
|
|
inst->src[0].negate ? brw_swap_cmod(inst->conditional_mod)
|
|
: inst->conditional_mod;
|
|
|
|
/* From the Kaby Lake PRM Vol. 7 "Assigning Conditional Flags":
|
|
*
|
|
* * Note that the [post condition signal] bits generated at
|
|
* the output of a compute are before the .sat.
|
|
*
|
|
* Paragraph about post_zero does not mention saturation, but
|
|
* testing it on actual GPUs shows that conditional modifiers are
|
|
* applied after saturation.
|
|
*
|
|
* * post_zero bit: This bit reflects whether the final
|
|
* result is zero after all the clamping, normalizing,
|
|
* or format conversion logic.
|
|
*
|
|
* For this reason, no additional restrictions are necessary on
|
|
* instructions with saturate.
|
|
*/
|
|
|
|
/* Otherwise, try propagating the conditional. */
|
|
if (scan_inst->can_do_cmod() &&
|
|
((!read_flag && scan_inst->conditional_mod == BRW_CONDITIONAL_NONE) ||
|
|
scan_inst->conditional_mod == cond)) {
|
|
scan_inst->conditional_mod = cond;
|
|
scan_inst->flag_subreg = inst->flag_subreg;
|
|
inst->remove();
|
|
progress = true;
|
|
}
|
|
break;
|
|
}
|
|
|
|
if ((scan_inst->flags_written(devinfo) & flags_written) != 0)
|
|
break;
|
|
|
|
read_flag = read_flag ||
|
|
(scan_inst->flags_read(devinfo) & flags_written) != 0;
|
|
}
|
|
}
|
|
|
|
return progress;
|
|
}
|
|
|
|
bool
|
|
brw_opt_cmod_propagation(brw_shader &s)
|
|
{
|
|
bool progress = false;
|
|
|
|
foreach_block_reverse(block, s.cfg) {
|
|
progress = opt_cmod_propagation_local(s.devinfo, block) || progress;
|
|
}
|
|
|
|
if (progress) {
|
|
s.invalidate_analysis(BRW_DEPENDENCY_INSTRUCTIONS);
|
|
}
|
|
|
|
return progress;
|
|
}
|