Georg Lehmann 54fa55a3f7 radv: don't use v_mqsad_u32_u8 on gfx7 ... According to tests on hawaii, v_mqsad_u32_u8 always uses saturating accumulation while v_msad_u8 truncates. GFX8+ can control this with the VOP3 clamp bit, on older hardware that's not supported. We want truncation for the NIR opcode. Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/12062 Fixes: c3c138b10f ("radv: optimize msad_4x8 to mqsad_4x8") Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31809>		2024-10-24 17:20:56 +00:00
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addrlib	ac: make sure VEGA20 and MI200 version ranges don't overlap with other chips	2024-09-27 19:21:55 +00:00
ci	ci: uprev vkd3d-proton to 59d6d4b5ed23766e69fe252408a3401d2fd52ce8	2024-10-23 15:47:54 +00:00
common	treewide: don't lower to LCSSA before calling nir_divergence_analysis()	2024-10-24 10:06:17 +00:00
compiler	aco/tests: add tests for VALUReadSGPRHazard	2024-10-24 16:08:08 +00:00
drm-shim	amd/drm-shim: add GFX1150 support	2024-08-13 13:17:17 +00:00
llvm	ac/llvm: cast to integer after derivative intrinsics	2024-10-24 11:23:07 +00:00
registers	amd: add gfx12 register definitions	2024-05-11 22:14:05 -04:00
vpelib	amd/vpelib: Add missing copyrights	2024-10-18 05:56:36 +00:00
vulkan	radv: don't use v_mqsad_u32_u8 on gfx7	2024-10-24 17:20:56 +00:00
meson.build	build: pass licensing information in SPDX form	2024-06-29 12:42:49 -07:00