Marek Olšák 53c64973e8 Inline _mesa_sha1_compute/format, remove the other unused ones ... _mesa_sha1_format has a few remaining uses, so it's moved to build_id.c, which is its last user. Acked-by: Alyssa Rosenzweig <alyssa.rosenzweig@intel.com> Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/40383>		2026-03-23 07:03:27 +00:00
..
addrlib	amd/addrlib: Add more GFX1013 GPUs	2026-03-16 09:40:41 +00:00
ci	radv/ci: update restricted trace checksum	2026-03-19 07:41:30 +00:00
common	Inline _mesa_sha1_init/update/final functions	2026-03-23 07:03:27 +00:00
compiler	nir: change export_amd intrinsics to use target instead of base	2026-03-23 06:10:49 +00:00
drm-shim	amd/drm-shim: enable conformant_trunc_coord for navi31	2026-03-17 10:27:07 +00:00
gmlib	meson: Relax -Wmaybe-uninitialized errors	2025-09-16 06:16:20 +00:00
lanczoslib	meson: Relax -Wmaybe-uninitialized errors	2025-09-16 06:16:20 +00:00
llvm	nir: change export_amd intrinsics to use target instead of base	2026-03-23 06:10:49 +00:00
packets	amd: generate a packet parser/printer automatically from packet definitions	2026-03-11 18:54:20 +00:00
registers	amd: Rename GFX1103_R1/R2 to PHOENIX/2	2024-11-20 02:14:40 +00:00
vpelib	amd/vpelib: Apply external CSC	2026-03-04 13:17:26 +08:00
vulkan	Inline _mesa_sha1_compute/format, remove the other unused ones	2026-03-23 07:03:27 +00:00
meson.build	radv/tests: require drm-shim and use it instead of RADV_FORCE_FAMILY	2025-11-19 07:11:05 +00:00