Tapani Pälli 4e80045ae0 intel/genxml/anv: fix the layout of call stack handler struct ... Patch adds new CALL_STACK_HANDLER struct which has offset to start and end of RegistersPerThread field, this spec changes is described in Wa_22019854901 (see HSD 22019967134). Signed-off-by: Tapani Pälli <tapani.palli@intel.com> Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33342>		2025-02-04 08:44:04 +00:00
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blorp	intel: Add meson option -Dintel-elk	2025-01-30 00:45:59 +00:00
ci	Uprev Piglit to fc8179d319046f45346bcbcc5aaeabebdf151f03	2025-01-31 20:36:33 +00:00
common	intel: Initialize upper 32bits of drm_xe_sync.handle	2025-02-02 21:34:45 -08:00
compiler	intel/brw: Remove 'fs' prefix from brw_from_nir functions	2025-02-03 23:08:11 +00:00
decoder	intel: Add meson option -Dintel-elk	2025-01-30 00:45:59 +00:00
dev	intel/brw: Use SHADER_OPCODE_SEND_GATHER in Xe3	2025-01-30 04:43:58 +00:00
ds	intel : Expose Shader hashes for utrace and Perfetto	2025-01-10 17:38:16 +00:00
executor	intel: Initialize upper 32bits of drm_xe_sync.handle	2025-02-02 21:34:45 -08:00
genxml	intel/genxml/anv: fix the layout of call stack handler struct	2025-02-04 08:44:04 +00:00
isl	isl: use workaround framework for Wa_1207137018	2025-01-29 12:10:13 +00:00
nullhw-layer	build: pass licensing information in SPDX form	2024-06-29 12:42:49 -07:00
perf	intel/perf: add new perf consts to support more metrics	2025-01-16 00:01:56 +00:00
shaders	intel: output a depfile with mesa_clc	2025-02-04 00:10:01 +00:00
tools	intel: Add meson option -Dintel-elk	2025-01-30 00:45:59 +00:00
vulkan	intel/genxml/anv: fix the layout of call stack handler struct	2025-02-04 08:44:04 +00:00
vulkan_hasvk	hasvk: disable logic op for float/srgb formats	2025-01-29 08:02:21 +00:00
meson.build	intel: Add meson option -Dintel-elk	2025-01-30 00:45:59 +00:00