fdo-mirrors/mesa
1
0
Fork 0
mirror of https://gitlab.freedesktop.org/mesa/mesa.git synced 2025-12-25 06:30:10 +01:00
Code Issues Projects Releases Packages Wiki Activity Actions 1

intel/genxml/anv: fix the layout of call stack handler struct

Browse source 
Patch adds new CALL_STACK_HANDLER struct which has offset to
start and end of RegistersPerThread field, this spec changes is
described in Wa_22019854901 (see HSD 22019967134).

Signed-off-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33342>
This commit is contained in:
Tapani Pälli 2025-01-28 13:43:49 +02:00 • committed by Marge Bot
parent 5b856a741d
commit 4e80045ae0
3 changed files with 52 additions and 0 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

26
src/intel/genxml/gen300_rt.xml
View file

@ -9,4 +9,30 @@
<field name="Kernel Start Pointer" start="6" end="31" type="offset" />
<field name="Registers Per Thread" start="60" end="63" type="uint" />
</struct>
<struct name="CALL_STACK_HANDLER" length="2">
<field name="Offset To Local Arguments" start="0" end="2" type="uint" />
<field name="Bindless Shader Dispatch Mode" start="4" end="4" type="uint">
<value name="RT_SIMD16" value="0" />
</field>
<field name="Kernel Start Pointer" start="6" end="31" type="offset" />
<field name="Registers Per Thread" start="59" end="62" type="uint" />
</struct>
<struct name="RT_DISPATCH_GLOBALS" length="20">
<field name="Mem Base Address" start="0" end="63" type="address" />
<field name="Call Stack Handler" start="64" end="127" type="CALL_STACK_HANDLER" />
<field name="Async RT Stack Size" start="128" end="159" type="uint" />
<field name="Num DSS RT Stacks" start="160" end="175" type="uint" />
<field name="Max BVH Levels" start="192" end="194" type="uint" />
<field name="Flags" start="224" end="224" type="uint">
<value name="RT_DEPTH_TEST_LESS_EQUAL" value="1" />
</field>
<field name="Hit Group Table" start="256" end="319" type="RT_SHADER_TABLE" />
<field name="Miss Group Table" start="320" end="383" type="RT_SHADER_TABLE" />
<field name="SW Stack Size" start="384" end="415" type="uint" />
<field name="Launch Width" start="416" end="447" type="uint" />
<field name="Launch Height" start="448" end="479" type="uint" />
<field name="Launch Depth" start="480" end="511" type="uint" />
<field name="Callable Group Table" start="512" end="575" type="RT_SHADER_TABLE" />
<field name="Resume Shader Table" start="576" end="639" type="address" />
</struct>
</genxml>

16
src/intel/vulkan/anv_genX.h
View file

@ -274,6 +274,22 @@ genX(compute_pipeline_emit)(struct anv_compute_pipeline *pipeline);
void
genX(ray_tracing_pipeline_emit)(struct anv_ray_tracing_pipeline *pipeline);
#if GFX_VERx10 >= 300
#define anv_shader_bin_get_handler(bin, local_arg_offset) ({ \
assert((local_arg_offset) % 8 == 0); \
const struct brw_bs_prog_data *prog_data = \
brw_bs_prog_data_const(bin->prog_data); \
assert(prog_data->simd_size == 16); \
\
(struct GENX(CALL_STACK_HANDLER)) { \
.OffsetToLocalArguments = (local_arg_offset) / 8, \
.BindlessShaderDispatchMode = RT_SIMD16, \
.KernelStartPointer = bin->kernel.offset, \
.RegistersPerThread = ptl_register_blocks(prog_data->base.grf_used), \
}; \
})
#endif
#if GFX_VERx10 >= 300
#define anv_shader_bin_get_bsr(bin, local_arg_offset) ({ \
assert((local_arg_offset) % 8 == 0); \

10
src/intel/vulkan/genX_cmd_compute.c
View file

@ -1031,8 +1031,13 @@ cmd_buffer_emit_rt_dispatch_globals(struct anv_cmd_buffer *cmd_buffer,
.bo = rt->scratch.bo,
.offset = rt->scratch.layout.ray_stack_start,
},
#if GFX_VERx10 == 300
.CallStackHandler = anv_shader_bin_get_handler(
cmd_buffer->device->rt_trivial_return, 0),
#else
.CallStackHandler = anv_shader_bin_get_bsr(
cmd_buffer->device->rt_trivial_return, 0),
#endif
.AsyncRTStackSize = rt->scratch.layout.ray_stack_stride / 64,
.NumDSSRTStacks = rt->scratch.layout.stack_ids_per_dss,
.MaxBVHLevels = BRW_RT_MAX_BVH_LEVELS,
@ -1079,8 +1084,13 @@ cmd_buffer_emit_rt_dispatch_globals_indirect(struct anv_cmd_buffer *cmd_buffer,
.bo = rt->scratch.bo,
.offset = rt->scratch.layout.ray_stack_start,
},
#if GFX_VERx10 == 300
.CallStackHandler = anv_shader_bin_get_handler(
cmd_buffer->device->rt_trivial_return, 0),
#else
.CallStackHandler = anv_shader_bin_get_bsr(
cmd_buffer->device->rt_trivial_return, 0),
#endif
.AsyncRTStackSize = rt->scratch.layout.ray_stack_stride / 64,
.NumDSSRTStacks = rt->scratch.layout.stack_ids_per_dss,
.MaxBVHLevels = BRW_RT_MAX_BVH_LEVELS,