Emma Anholt 37b544e410 hasvk: Fix gfx8/9 VB range > 32bits workaround detection. ... Since the dirty range started out as 0..0, you would have 0..VBend as the new dirty range on the first draw, and if your VB was >32b then you'd flush every time you used it. Instead, if there's no existing dirty range then just set it to our new VB's range. Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21370>		2023-02-18 07:25:47 +00:00
..
blorp	intel/blorp: disable REP16 for gfx12+ with R10G10B10_FLOAT_A2	2023-02-09 06:34:43 +00:00
ci	ci: enable dEQP-VK.ubo.random.all_shared_buffer.48	2023-02-16 23:31:59 +00:00
common	intel/common: Move i915 files to i915 folder	2023-02-16 16:24:36 +00:00
compiler	intel/nir: Use nir_lower_mem_access_bit_sizes()	2023-02-17 00:55:54 +00:00
dev	intel/dev: add a default urb value for intel_stub_gpu on dg2	2023-02-13 09:38:06 +00:00
ds	intel/ds: track end of pipe bits	2023-02-06 09:12:18 +00:00
genxml	intel/genxml: add missing power well control bits	2023-02-08 02:56:28 +00:00
isl	isl: fix some documentation	2023-02-14 16:55:21 +00:00
nullhw-layer	vulkan/layers: Use PUBLIC instead of VK_LAYER_EXPORT	2023-02-17 03:42:34 +00:00
perf	intel/perf: also add the oa timestamp shift on MTL	2023-02-17 12:10:05 +00:00
tools	anv,hasvk: migrate align32 to the right functions from util	2023-01-06 17:22:16 +00:00
vulkan	anv: Fix gfx8/9 VB range > 32bits workaround detection.	2023-02-18 07:25:47 +00:00
vulkan_hasvk	hasvk: Fix gfx8/9 VB range > 32bits workaround detection.	2023-02-18 07:25:47 +00:00
meson.build	intel: Disable SSE2 instruction set if building for non x86 architectures	2022-11-23 16:57:23 +00:00