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7b7fb811ab
Signed-off-by: Simon Perretta <simon.perretta@imgtec.com> Acked-by: Erik Faye-Lund <erik.faye-lund@collabora.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37439>
131 lines
3 KiB
C
131 lines
3 KiB
C
/*
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* Copyright © 2025 Imagination Technologies Ltd.
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* SPDX-License-Identifier: MIT
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*/
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#ifndef PVR_IFACE_H
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#define PVR_IFACE_H
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/**
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* \file pvr_iface.h
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*
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* \brief USC program interface.
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*/
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/** Query availability shader data; shared registers. */
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enum pvr_query_availability_data {
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PVR_QUERY_AVAILABILITY_DATA_INDEX_COUNT,
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PVR_QUERY_AVAILABILITY_DATA_INDEX_BO_LO,
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PVR_QUERY_AVAILABILITY_DATA_INDEX_BO_HI,
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PVR_QUERY_AVAILABILITY_DATA_BO_LO,
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PVR_QUERY_AVAILABILITY_DATA_BO_HI,
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_PVR_QUERY_AVAILABILITY_DATA_COUNT,
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};
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/** Query copy shader data; shared registers. */
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enum pvr_query_copy_data {
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PVR_QUERY_COPY_DATA_INDEX_COUNT,
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PVR_QUERY_COPY_DATA_DEST_BO_LO,
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PVR_QUERY_COPY_DATA_DEST_BO_HI,
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PVR_QUERY_COPY_DATA_AVAILABILITY_BO_LO,
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PVR_QUERY_COPY_DATA_AVAILABILITY_BO_HI,
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PVR_QUERY_COPY_DATA_RESULT_BO_LO,
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PVR_QUERY_COPY_DATA_RESULT_BO_HI,
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PVR_QUERY_COPY_DATA_DEST_STRIDE,
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PVR_QUERY_COPY_DATA_FLAGS,
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_PVR_QUERY_COPY_DATA_COUNT,
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};
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/** Query reset shader data; shared registers. */
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enum pvr_query_reset_data {
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PVR_QUERY_RESET_DATA_INDEX_COUNT,
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PVR_QUERY_RESET_DATA_RESULT_BO_LO,
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PVR_QUERY_RESET_DATA_RESULT_BO_HI,
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PVR_QUERY_RESET_DATA_AVAILABILITY_BO_LO,
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PVR_QUERY_RESET_DATA_AVAILABILITY_BO_HI,
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_PVR_QUERY_RESET_DATA_COUNT,
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};
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/** Clear attachment shader data; shared registers. */
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enum pvr_clear_attach_data {
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PVR_CLEAR_ATTACH_DATA_DWORD0,
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PVR_CLEAR_ATTACH_DATA_DWORD1,
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PVR_CLEAR_ATTACH_DATA_DWORD2,
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PVR_CLEAR_ATTACH_DATA_DWORD3,
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PVR_CLEAR_ATTACH_DATA_TILE_ADDR_LO,
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PVR_CLEAR_ATTACH_DATA_TILE_ADDR_HI,
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_PVR_CLEAR_ATTACH_DATA_COUNT,
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};
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/** SPM load shader data; shared registers. */
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enum pvr_spm_load_data {
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PVR_SPM_LOAD_DATA_SMP = 0,
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PVR_SPM_LOAD_DATA_REG_TEX = 4,
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PVR_SPM_LOAD_DATA_BUF_TEX_0 = 8,
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PVR_SPM_LOAD_DATA_BUF_ADDR_0 = 12,
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PVR_SPM_LOAD_DATA_BUF_ADDR_1 = 14,
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PVR_SPM_LOAD_DATA_BUF_TEX_1 = 16,
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PVR_SPM_LOAD_DATA_BUF_TEX_2 = 20,
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PVR_SPM_LOAD_DATA_BUF_ADDR_2 = 24,
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PVR_SPM_LOAD_DATA_BUF_ADDR_3 = 26,
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PVR_SPM_LOAD_DATA_BUF_TEX_3 = 28,
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PVR_SPM_LOAD_DATA_BUF_TEX_4 = 32,
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PVR_SPM_LOAD_DATA_BUF_ADDR_4 = 36,
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PVR_SPM_LOAD_DATA_BUF_ADDR_5 = 38,
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PVR_SPM_LOAD_DATA_BUF_TEX_5 = 40,
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PVR_SPM_LOAD_DATA_BUF_TEX_6 = 44,
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PVR_SPM_LOAD_DATA_BUF_ADDR_6 = 48,
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_PVR_SPM_LOAD_DATA_COUNT = 50,
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};
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/** Load/store sr shader data; vertex input registers. */
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enum pvr_load_store_sr_data {
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PVR_LOAD_STORE_SR_DATA_SIZE_ADDR_LO,
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PVR_LOAD_STORE_SR_DATA_SIZE_ADDR_HI,
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PVR_LOAD_STORE_SR_DATA_STORE_ADDR_LO,
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PVR_LOAD_STORE_SR_DATA_STORE_ADDR_HI,
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_PVR_LOAD_STORE_SR_DATA_COUNT,
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};
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/** IDFWDF shader data; shared registers. */
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enum pvr_idfwdf_sr_data {
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PVR_IDFWDF_DATA_TEX = 0,
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PVR_IDFWDF_DATA_SMP = 4,
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PVR_IDFWDF_DATA_ADDR_LO,
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PVR_IDFWDF_DATA_ADDR_HI,
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_PVR_IDFWDF_DATA_COUNT,
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};
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#define PVR_IDFWDF_TEX_FORMAT VK_FORMAT_R32G32B32A32_SFLOAT
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#define PVR_IDFWDF_TEX_WIDTH 4U
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#define PVR_IDFWDF_TEX_HEIGHT 2U
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#define PVR_IDFWDF_TEX_STRIDE 4U
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#endif /* PVR_IFACE_H */
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