mesa/src/intel
Lionel Landwerlin a50d2fdb46 intel/fs: avoid cmod optimization on instruction with different write_mask
I've been running into failures with tests like :

dEQP-VK.robustness.robustness2.bind.notemplate.rgba32i.unroll.nonvolatile.uniform_buffer_dynamic.no_fmt_qual.len_4.samples_1.1d.frag

With the load_global_const_block_intel NIR intrinsic, you can load a
vec8/vec16 with a predicate. The predicate is correctly uniformized to
feed into the SEND instruction's flag register.

The problem is that a series of optimization first remove the
find_live_channel and then changes the broadcast into a simple MOV
instruction, on the assumption that the first channel is always active
if there is not control flow. This is correct.

But after that the cmod optimzation will remove this instruction :

   mov.nz.f0.0(16) null:D, vgrf16+0.0<0>:D NoMask

because it seems to be equivalent to :

   cmp.g.f0.0(16) vgrf16:D, vgrf12:D, 63d

In this case vgrf16 is the predicate to the load block SEND
instruction. Since the execution mask is different between both, some
of the channels of the SEND instruction end up not being loaded or
loaded with the wrong predication and we end up with incorrect UBO
data.

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Cc: mesa-stable
Reviewed-by: Marcin Ślusarz <marcin.slusarz@intel.com>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20852>
2023-01-24 07:35:42 +00:00
..
blorp intel/blorp: Lower base_workgroup_id to zero 2023-01-18 12:21:03 +00:00
ci ci/piglit: Add some common piglit skips for Mesa CI's testing of glx. 2023-01-24 00:13:02 +00:00
common intel: use a shared UUID with other drivers 2023-01-17 17:36:07 +02:00
compiler intel/fs: avoid cmod optimization on instruction with different write_mask 2023-01-24 07:35:42 +00:00
dev intel/dev: Split hwconfig i915 specific code 2023-01-20 17:26:08 +00:00
ds intel/utrace: document tracepoints 2023-01-13 01:22:15 +00:00
genxml intel/genxml: Drop CACHE_MODE_SS definition. 2023-01-12 21:48:40 +00:00
isl intel/isl: Disable CCS on MTL until B0 (Wa_14017353530) 2022-12-15 11:43:00 -08:00
nullhw-layer utils: Merge util/debug.* into util/u_debug.* and remove util/debug.* 2022-11-02 07:25:39 +00:00
perf intel: add MTL performance metrics 2022-12-09 09:13:02 +00:00
tools anv,hasvk: migrate align32 to the right functions from util 2023-01-06 17:22:16 +00:00
vulkan anv: fix preemption enable emission in gpu_memcpy 2023-01-20 22:35:41 +02:00
vulkan_hasvk hasvk: check the return value of anv_execbuf_add_bo_bitset() 2023-01-23 20:43:36 +00:00
meson.build intel: Disable SSE2 instruction set if building for non x86 architectures 2022-11-23 16:57:23 +00:00