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Increases GPR pressure somehow but it's obviously the right thing to do. SIMD16: Totals: Instrs: 2767536 -> 2767381 (-0.01%); split: -0.01%, +0.00% CodeSize: 44323392 -> 40075680 (-9.58%); split: -9.58%, +0.00% Totals from 2147 (81.11% of 2647) affected shaders: Instrs: 2704498 -> 2704343 (-0.01%); split: -0.01%, +0.00% CodeSize: 43477568 -> 39229856 (-9.77%); split: -9.77%, +0.00% SIMD32: Totals: Instrs: 4731031 -> 4746775 (+0.33%); split: -0.33%, +0.67% CodeSize: 76609152 -> 70004080 (-8.62%); split: -8.68%, +0.06% Number of spill instructions: 50110 -> 50187 (+0.15%); split: -0.00%, +0.16% Number of fill instructions: 51341 -> 51804 (+0.90%); split: -0.00%, +0.91% Totals from 2136 (80.70% of 2647) affected shaders: Instrs: 4666677 -> 4682421 (+0.34%); split: -0.34%, +0.67% CodeSize: 75735136 -> 69130064 (-8.72%); split: -8.78%, +0.06% Number of spill instructions: 50108 -> 50185 (+0.15%); split: -0.00%, +0.16% Number of fill instructions: 51339 -> 51802 (+0.90%); split: -0.00%, +0.91% Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@intel.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/41215> |
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| .. | ||
| brw | ||
| elk | ||
| jay | ||
| brw_device_sha1_gen_c.py | ||
| brw_list.h | ||
| intel_gfx_ver_enum.h | ||
| intel_nir.c | ||
| intel_nir.h | ||
| intel_nir_blockify_uniform_loads.c | ||
| intel_nir_clamp_image_1d_2d_array_sizes.c | ||
| intel_nir_clamp_per_vertex_loads.c | ||
| intel_nir_lower_non_uniform_barycentric_at_sample.c | ||
| intel_nir_lower_non_uniform_resource_intel.c | ||
| intel_nir_lower_printf.c | ||
| intel_nir_lower_shading_rate_output.c | ||
| intel_nir_lower_sparse.c | ||
| intel_nir_opt_peephole_ffma.c | ||
| intel_nir_opt_peephole_imul32x16.c | ||
| intel_nir_tcs_workarounds.c | ||
| intel_prim.h | ||
| intel_shader_enums.h | ||
| meson.build | ||