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export SEARCH_PATH="src/intel src/gallium/drivers/iris src/mesa/drivers/dri/i965" grep -E "gen_device" -rIl $SEARCH_PATH | xargs sed -ie "s/gen_device/intel_device/g" Signed-off-by: Anuj Phogat <anuj.phogat@gmail.com> Reviewed-by: Kenneth Graunke <kenneth@whitecape.org> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10241>
102 lines
2.9 KiB
C
102 lines
2.9 KiB
C
#ifndef AUBINATOR_VIEWER_H
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#define AUBINATOR_VIEWER_H
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#include "imgui/imgui.h"
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#include "common/intel_decoder.h"
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#include "common/intel_disasm.h"
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struct aub_viewer_cfg {
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ImColor clear_color;
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ImColor dwords_color;
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ImColor highlight_color;
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ImColor error_color;
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ImColor missing_color;
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ImColor boolean_color;
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aub_viewer_cfg() :
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clear_color(114, 144, 154),
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dwords_color(29, 177, 194, 255),
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highlight_color(0, 230, 0, 255),
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error_color(236, 255, 0, 255),
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missing_color(230, 0, 230, 255),
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boolean_color(228, 75, 255) {}
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};
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struct aub_viewer_decode_cfg {
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struct ImGuiTextFilter command_filter;
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struct ImGuiTextFilter field_filter;
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bool drop_filtered;
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bool show_dwords;
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aub_viewer_decode_cfg() :
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drop_filtered(false),
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show_dwords(true) {}
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};
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enum aub_decode_stage {
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AUB_DECODE_STAGE_VS,
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AUB_DECODE_STAGE_HS,
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AUB_DECODE_STAGE_DS,
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AUB_DECODE_STAGE_GS,
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AUB_DECODE_STAGE_PS,
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AUB_DECODE_STAGE_CS,
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AUB_DECODE_N_STAGE,
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};
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struct aub_decode_urb_stage_state {
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uint32_t start;
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uint32_t size;
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uint32_t n_entries;
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uint32_t const_rd_length;
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uint32_t rd_offset;
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uint32_t rd_length;
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uint32_t wr_offset;
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uint32_t wr_length;
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};
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struct aub_viewer_decode_ctx {
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struct intel_batch_decode_bo (*get_bo)(void *user_data, bool ppgtt, uint64_t address);
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unsigned (*get_state_size)(void *user_data,
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uint32_t offset_from_dynamic_state_base_addr);
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void (*display_shader)(void *user_data, const char *shader_desc, uint64_t address);
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void (*display_urb)(void *user_data, const struct aub_decode_urb_stage_state *stages);
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void (*edit_address)(void *user_data, uint64_t address, uint32_t length);
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void *user_data;
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const struct intel_device_info *devinfo;
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struct intel_spec *spec;
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enum drm_i915_gem_engine_class engine;
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struct aub_viewer_cfg *cfg;
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struct aub_viewer_decode_cfg *decode_cfg;
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uint64_t surface_base;
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uint64_t dynamic_base;
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uint64_t instruction_base;
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enum aub_decode_stage stage;
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uint32_t end_urb_offset;
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struct aub_decode_urb_stage_state urb_stages[AUB_DECODE_N_STAGE];
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int n_batch_buffer_start;
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};
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void aub_viewer_decode_ctx_init(struct aub_viewer_decode_ctx *ctx,
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struct aub_viewer_cfg *cfg,
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struct aub_viewer_decode_cfg *decode_cfg,
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const struct intel_device_info *devinfo,
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struct intel_spec *spec,
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struct intel_batch_decode_bo (*get_bo)(void *, bool, uint64_t),
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unsigned (*get_state_size)(void *, uint32_t),
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void *user_data);
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void aub_viewer_render_batch(struct aub_viewer_decode_ctx *ctx,
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const void *batch, uint32_t batch_size,
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uint64_t batch_addr, bool from_ring);
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#endif /* AUBINATOR_VIEWER_H */
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