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mesa/src/intel/compiler
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Matt Turner 2eeb1b0ad9 i965: Use correct VertStride on align16 instructions. 
In commit c35fa7a, we changed the "width" of DF source registers to 2,
which is conceptually fine. Unfortunately a VertStride of 2 is not
allowed by align16 instructions on IVB/BYT, and the regular VertStride
of 4 works fine in any case.

See generated_tests/spec/arb_gpu_shader_fp64/execution/built-in-functions/vs-round-double.shader_test
for example:

cmp.ge.f0(8)    g18<1>DF        g1<0>.xyxyDF    -g8<2>DF        { align16 1Q };
        ERROR: In Align16 mode, only VertStride of 0 or 4 is allowed
cmp.ge.f0(8)    g19<1>DF        g1<0>.xyxyDF    -g9<2>DF        { align16 2N };
        ERROR: In Align16 mode, only VertStride of 0 or 4 is allowed

v2:
- Add spec quote (Curro).
- Change the condition to only BRW_VERTICAL_STRIDE_2 (Curro)

Reviewed-by: Samuel Iglesias Gonsálvez <siglesias@igalia.com>
Reviewed-by: Francisco Jerez <currojerez@riseup.net>
2017-04-14 14:56:09 -07:00
..
.gitignore i965: Move the back-end compiler to src/intel/compiler 2017-03-13 11:16:34 +00:00
brw_cfg.cpp i965: Move the back-end compiler to src/intel/compiler 2017-03-13 11:16:34 +00:00
brw_cfg.h intel/compiler: consistently use ifndef guards over pragma once 2017-03-22 16:55:22 +00:00
brw_compiler.c i965: Move the back-end compiler to src/intel/compiler 2017-03-13 11:16:34 +00:00
brw_compiler.h anv/pipeline: make FragCoord include sample positions when sample shading 2017-03-24 08:11:53 +01:00
brw_dead_control_flow.cpp i965: Move the back-end compiler to src/intel/compiler 2017-03-13 11:16:34 +00:00
brw_dead_control_flow.h intel/compiler: consistently use ifndef guards over pragma once 2017-03-22 16:55:22 +00:00
brw_disasm.c i965/disasm: also print nibctrl in IVB for execsize=8 2017-04-14 14:56:06 -07:00
brw_eu.c i965: Move the back-end compiler to src/intel/compiler 2017-03-13 11:16:34 +00:00
brw_eu.h i965: Move the back-end compiler to src/intel/compiler 2017-03-13 11:16:34 +00:00
brw_eu_compact.c i965: Move the back-end compiler to src/intel/compiler 2017-03-13 11:16:34 +00:00
brw_eu_defines.h i965/vec4: split VEC4_OPCODE_FROM_DOUBLE into one opcode per destination's type 2017-04-14 14:56:08 -07:00
brw_eu_emit.c i965: Use correct VertStride on align16 instructions. 2017-04-14 14:56:09 -07:00
brw_eu_util.c intel/compiler: whitespace cleanups 2017-03-13 11:16:35 +00:00
brw_eu_validate.c i965: Handle IVB DF differences in the validator. 2017-04-14 14:56:07 -07:00
brw_fs.cpp i965/fs: lower all non-force_writemask_all DF instructions to SIMD4 on IVB/BYT 2017-04-14 14:56:08 -07:00
brw_fs.h i965/fs: rename lower_d2x to lower_conversions 2017-04-14 14:56:07 -07:00
brw_fs_builder.h i965: Move the back-end compiler to src/intel/compiler 2017-03-13 11:16:34 +00:00
brw_fs_cmod_propagation.cpp i965: Move the back-end compiler to src/intel/compiler 2017-03-13 11:16:34 +00:00
brw_fs_combine_constants.cpp i965: Move the back-end compiler to src/intel/compiler 2017-03-13 11:16:34 +00:00
brw_fs_copy_propagation.cpp i965: Move the back-end compiler to src/intel/compiler 2017-03-13 11:16:34 +00:00
brw_fs_cse.cpp i965: Move the back-end compiler to src/intel/compiler 2017-03-13 11:16:34 +00:00
brw_fs_dead_code_eliminate.cpp i965: Move the back-end compiler to src/intel/compiler 2017-03-13 11:16:34 +00:00
brw_fs_generator.cpp i965/fs: Get 64-bit indirect moves working on IVB. 2017-04-14 14:56:08 -07:00
brw_fs_live_variables.cpp i965: Move the back-end compiler to src/intel/compiler 2017-03-13 11:16:34 +00:00
brw_fs_live_variables.h intel/compiler: consistently use ifndef guards over pragma once 2017-03-22 16:55:22 +00:00
brw_fs_lower_conversions.cpp i965/fs: rename lower_d2x to lower_conversions 2017-04-14 14:56:07 -07:00
brw_fs_lower_pack.cpp i965: Move the back-end compiler to src/intel/compiler 2017-03-13 11:16:34 +00:00
brw_fs_nir.cpp i965/fs: Always provide a default LOD of 0 for TXS and TXL 2017-04-04 18:33:35 -07:00
brw_fs_reg_allocate.cpp i965/fs: Take into account lower frequency of conditional blocks in spilling cost heuristic. 2017-04-11 15:28:54 -07:00
brw_fs_register_coalesce.cpp i965: Move the back-end compiler to src/intel/compiler 2017-03-13 11:16:34 +00:00
brw_fs_saturate_propagation.cpp i965: Move the back-end compiler to src/intel/compiler 2017-03-13 11:16:34 +00:00
brw_fs_sel_peephole.cpp Revert "i965/fs: Don't emit SEL instructions for type-converting MOVs." 2017-04-14 14:56:07 -07:00
brw_fs_surface_builder.cpp i965: Move the back-end compiler to src/intel/compiler 2017-03-13 11:16:34 +00:00
brw_fs_surface_builder.h i965: Move the back-end compiler to src/intel/compiler 2017-03-13 11:16:34 +00:00
brw_fs_validate.cpp i965: Move the back-end compiler to src/intel/compiler 2017-03-13 11:16:34 +00:00
brw_fs_visitor.cpp i965: Move the back-end compiler to src/intel/compiler 2017-03-13 11:16:34 +00:00
brw_inst.h i965: Move the back-end compiler to src/intel/compiler 2017-03-13 11:16:34 +00:00
brw_interpolation_map.c i965: Move the back-end compiler to src/intel/compiler 2017-03-13 11:16:34 +00:00
brw_ir_allocator.h i965: Move the back-end compiler to src/intel/compiler 2017-03-13 11:16:34 +00:00
brw_ir_fs.h i965/fs: add helper to retrieve instruction execution type 2017-04-14 14:56:07 -07:00
brw_ir_vec4.h i965/vec4: don't do horizontal stride on some register file types 2017-04-14 14:56:09 -07:00
brw_nir.c i965: Replace OPT_V() with OPT(). 2017-03-23 14:34:44 -07:00
brw_nir.h intel/compiler: consistently use ifndef guards over pragma once 2017-03-22 16:55:22 +00:00
brw_nir_analyze_boolean_resolves.c i965: Move the back-end compiler to src/intel/compiler 2017-03-13 11:16:34 +00:00
brw_nir_attribute_workarounds.c nir: Rework conversion opcodes 2017-03-14 07:36:40 -07:00
brw_nir_intrinsics.c i965: Move the back-end compiler to src/intel/compiler 2017-03-13 11:16:34 +00:00
brw_nir_opt_peephole_ffma.c i965: Move the back-end compiler to src/intel/compiler 2017-03-13 11:16:34 +00:00
brw_nir_tcs_workarounds.c i965: Move the back-end compiler to src/intel/compiler 2017-03-13 11:16:34 +00:00
brw_nir_trig_workarounds.py i965: Move the back-end compiler to src/intel/compiler 2017-03-13 11:16:34 +00:00
brw_packed_float.c i965: Move the back-end compiler to src/intel/compiler 2017-03-13 11:16:34 +00:00
brw_predicated_break.cpp i965: Move the back-end compiler to src/intel/compiler 2017-03-13 11:16:34 +00:00
brw_reg.h i965/fs: add helper to retrieve instruction execution type 2017-04-14 14:56:07 -07:00
brw_schedule_instructions.cpp i965: Move the back-end compiler to src/intel/compiler 2017-03-13 11:16:34 +00:00
brw_shader.cpp i965/vec4: split VEC4_OPCODE_FROM_DOUBLE into one opcode per destination's type 2017-04-14 14:56:08 -07:00
brw_shader.h intel/compiler: consistently use ifndef guards over pragma once 2017-03-22 16:55:22 +00:00
brw_vec4.cpp i965/vec4: split VEC4_OPCODE_FROM_DOUBLE into one opcode per destination's type 2017-04-14 14:56:08 -07:00
brw_vec4.h i965/vec4: use vec4_builder to emit instructions in setup_imm_df() 2017-04-14 14:56:09 -07:00
brw_vec4_builder.h i965: Move the back-end compiler to src/intel/compiler 2017-03-13 11:16:34 +00:00
brw_vec4_cmod_propagation.cpp i965: Move the back-end compiler to src/intel/compiler 2017-03-13 11:16:34 +00:00
brw_vec4_copy_propagation.cpp i965/vec4: split VEC4_OPCODE_FROM_DOUBLE into one opcode per destination's type 2017-04-14 14:56:08 -07:00
brw_vec4_cse.cpp i965: Move the back-end compiler to src/intel/compiler 2017-03-13 11:16:34 +00:00
brw_vec4_dead_code_eliminate.cpp i965/vec4/dce: improve track of partial flag register writes 2017-04-14 14:56:09 -07:00
brw_vec4_generator.cpp i965/vec4: Fix exec size for MOVs {SET,PICK}_{HIGH,LOW}_32BIT. 2017-04-14 14:56:09 -07:00
brw_vec4_gs_nir.cpp i965: Move the back-end compiler to src/intel/compiler 2017-03-13 11:16:34 +00:00
brw_vec4_gs_visitor.cpp i965: Move the back-end compiler to src/intel/compiler 2017-03-13 11:16:34 +00:00
brw_vec4_gs_visitor.h i965: Move the back-end compiler to src/intel/compiler 2017-03-13 11:16:34 +00:00
brw_vec4_live_variables.cpp i965: Move the back-end compiler to src/intel/compiler 2017-03-13 11:16:34 +00:00
brw_vec4_live_variables.h i965/vec4: consider subregister offset in live variables 2017-04-14 14:56:08 -07:00
brw_vec4_nir.cpp i965/vec4: use vec4_builder to emit instructions in setup_imm_df() 2017-04-14 14:56:09 -07:00
brw_vec4_reg_allocate.cpp i965/vec4: split VEC4_OPCODE_FROM_DOUBLE into one opcode per destination's type 2017-04-14 14:56:08 -07:00
brw_vec4_surface_builder.cpp i965: Move the back-end compiler to src/intel/compiler 2017-03-13 11:16:34 +00:00
brw_vec4_surface_builder.h i965: Move the back-end compiler to src/intel/compiler 2017-03-13 11:16:34 +00:00
brw_vec4_tcs.cpp i965: Move the back-end compiler to src/intel/compiler 2017-03-13 11:16:34 +00:00
brw_vec4_tcs.h i965: Move the back-end compiler to src/intel/compiler 2017-03-13 11:16:34 +00:00
brw_vec4_tes.cpp i965: Move the back-end compiler to src/intel/compiler 2017-03-13 11:16:34 +00:00
brw_vec4_tes.h i965: Move the back-end compiler to src/intel/compiler 2017-03-13 11:16:34 +00:00
brw_vec4_visitor.cpp i965: Move the back-end compiler to src/intel/compiler 2017-03-13 11:16:34 +00:00
brw_vec4_vs.h i965: Move the back-end compiler to src/intel/compiler 2017-03-13 11:16:34 +00:00
brw_vec4_vs_visitor.cpp i965: Move the back-end compiler to src/intel/compiler 2017-03-13 11:16:34 +00:00
brw_vue_map.c i965: Move the back-end compiler to src/intel/compiler 2017-03-13 11:16:34 +00:00
brw_wm_iz.cpp intel/compiler: whitespace cleanups 2017-03-13 11:16:35 +00:00
gen6_gs_visitor.cpp i965: Move the back-end compiler to src/intel/compiler 2017-03-13 11:16:34 +00:00
gen6_gs_visitor.h i965: Move the back-end compiler to src/intel/compiler 2017-03-13 11:16:34 +00:00
intel_asm_annotation.c i965: Move the back-end compiler to src/intel/compiler 2017-03-13 11:16:34 +00:00
intel_asm_annotation.h i965: Move the back-end compiler to src/intel/compiler 2017-03-13 11:16:34 +00:00
test_eu_compact.cpp intel/compiler: link all tests again gtest, even test_eu_compact" 2017-03-13 11:16:35 +00:00
test_eu_validate.cpp i965: Move the back-end compiler to src/intel/compiler 2017-03-13 11:16:34 +00:00
test_fs_cmod_propagation.cpp i965: Move the back-end compiler to src/intel/compiler 2017-03-13 11:16:34 +00:00
test_fs_copy_propagation.cpp i965: Move the back-end compiler to src/intel/compiler 2017-03-13 11:16:34 +00:00
test_fs_saturate_propagation.cpp i965: Move the back-end compiler to src/intel/compiler 2017-03-13 11:16:34 +00:00
test_vec4_cmod_propagation.cpp i965: Move the back-end compiler to src/intel/compiler 2017-03-13 11:16:34 +00:00
test_vec4_copy_propagation.cpp i965: Move the back-end compiler to src/intel/compiler 2017-03-13 11:16:34 +00:00
test_vec4_register_coalesce.cpp i965: Move the back-end compiler to src/intel/compiler 2017-03-13 11:16:34 +00:00
test_vf_float_conversions.cpp i965: Move the back-end compiler to src/intel/compiler 2017-03-13 11:16:34 +00:00