Danylo Piliaiev b8d486f298 nir/algebraic: Separate has_dot_4x8 into has_sdot_4x8 and has_udot_4x8 ... Adreno GPUs has native instruction for unsigned and mixed dot_4x8 but not signed dot product. Signed-off-by: Danylo Piliaiev <dpiliaiev@igalia.com> Reviewed-by: Rhys Perry <pendingchaos02@gmail.com> Reviewed-by: Emma Anholt <emma@anholt.net> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13986>		2022-01-10 13:20:39 +02:00
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blorp	intel/blorp: Modify get_fast_clear_rect for XeHP	2021-12-11 04:14:20 +00:00
ci	anv/ci: Test with deqp-vk on Tiger Lake	2022-01-07 13:33:32 +00:00
common	intel/l3: Make DG1 urb-size exception more generic	2021-12-11 00:09:50 +00:00
compiler	nir/algebraic: Separate has_dot_4x8 into has_sdot_4x8 and has_udot_4x8	2022-01-10 13:20:39 +02:00
dev	intel/dev: Implement DG2 restrictions requiring additional DSSes to be disabled.	2022-01-07 07:58:27 +00:00
ds	intel: move timestamp scaling helper to intel/perf	2021-11-22 11:52:46 +00:00
genxml	intel/genxml/gen4-5: fix more Raster Operation in BLT to be a uint	2021-12-30 11:40:33 +10:00
isl	intel/isl: Require aux map for some 64K alignment	2021-12-11 04:14:20 +00:00
nullhw-layer	intel/nullhw: fix build	2021-03-26 20:12:40 +00:00
perf	intel: move timestamp scaling helper to intel/perf	2021-11-22 11:52:46 +00:00
tools	intel/stub: Implement shell versions of DRM_I915_GEM_GET_TILING and DRM_I915_SEM_GET_TILING	2021-12-16 23:06:38 +00:00
vulkan	anv: limit compiler valid color outputs using NIR variables	2022-01-10 09:38:32 +02:00
Makefile.perf.am	intel: Rename GEN_PERF prefix to INTEL_PERF in build files	2021-04-20 20:06:34 +00:00
meson.build	pps: Intel pps driver	2021-05-18 14:28:48 +00:00