Danylo Piliaiev e6f5480180 ir3: Add cat7 sleep instruction ... Has short and long variants, long seem to be ~20 times longer. The exact difference between it and a bunch of nops is unknown. The emission of this instruction were not observed in the wild. Signed-off-by: Danylo Piliaiev <dpiliaiev@igalia.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14419>		2023-02-21 19:59:14 +00:00
..
encode.c	ir3, isaspec: add raw instruction to assembler/disassembler.	2023-01-26 14:26:11 +00:00
ir3-cat0.xml	ir3: Make shift operand 64-bit.	2021-12-22 01:19:46 +00:00
ir3-cat1.xml	freedreno/isa: Add immed reg accessors	2021-10-15 15:52:33 +00:00
ir3-cat2.xml	ir3: Add support for (dis)assembling flat.b	2021-11-04 02:59:28 +00:00
ir3-cat3.xml	ir3: New cat3 instructions	2022-01-10 13:20:39 +02:00
ir3-cat4.xml	freedreno/isa: Convert to srcs/dsts	2021-06-23 17:20:29 +00:00
ir3-cat5.xml	ir3: Add cat5/cat7 cache related instructions	2023-02-21 19:59:14 +00:00
ir3-cat6.xml	ir3: Implement and document ldc.k	2022-03-17 12:15:45 +00:00
ir3-cat7.xml	ir3: Add cat7 sleep instruction	2023-02-21 19:59:14 +00:00
ir3-common.xml	freedreno/isa: Fix ldg/stg "halfness"	2021-10-19 16:04:42 +00:00
ir3-disasm.c	freedreno/isa: decode: switch bitmask_t to BITSET_WORD's	2021-09-21 20:25:31 +00:00
ir3.xml	freedreno/isa: Convert to srcs/dsts	2021-06-23 17:20:29 +00:00
isa.h	isaspec: Move isa_decode(..) declaration	2022-09-03 19:26:04 +00:00
meson.build	isaspec: Stop depending on glue headers and out-of-folder C files	2023-01-05 18:21:02 +00:00