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mesa/src/freedreno
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Danylo Piliaiev cbfb7e930d ir3/lower_tex_prefetch: Fix crash with lowered load_barycentric_at_offset 
ir3_nir_lower_tex_prefetch expects src0 of load_interpolated_input to
be intrinsic, however this assumption broke when src0 is
load_barycentric_at_offset and is lowered in series of alu instructions.

 32x2  %1121 = @load_barycentric_at_offset (%1120) (interp_mode=0)
 32x4  %1118 = @load_interpolated_input (%1121, %1116 (0x0)) ...
 32x2    %32 = vec2 %1118.x, %1118.y
 32x4    %37 = (float32)tex %36 (texture_handle), %34 (sampler_handle), %32 (coord), 0 (texture), 0 (sampler)

is lowered into:

 [...]
 32      %54 = ffma %46.y, %52, %50
 32      %55 = ffma %46.y, %53, %51
 32x2    %56 = vec2 %54, %55
 32x4    %57 = @load_interpolated_input (%56, %25 (0x0))
 [...]

Crash backtrace:

 #5  in __GI___assert_fail (assertion=0x7ff6692328 "parent && parent->type == nir_instr_type_intrinsic",
     file=0x7ff66921c8 "nir.h", line=2536, function=0x7ff6692630 <__PRETTY_FUNCTION__.13> "nir_instr_as_intrinsic")
     at assert.c:101
 #6  in nir_instr_as_intrinsic (parent=0x7fd4b648e8) at nir.h:2536
 #7  in coord_offset (ssa=0x7fd4b649d0) at ir3_nir_lower_tex_prefetch.c:77
 #8  in coord_offset (ssa=0x7fd4b64a90) at ir3_nir_lower_tex_prefetch.c:48
 #9  in ir3_nir_coord_offset (ssa=0x7fd4b64a90) at ir3_nir_lower_tex_prefetch.c:104
 #10 in lower_tex_prefetch_block (block=0x7fd482c100) at ir3_nir_lower_tex_prefetch.c:185
 #11 in lower_tex_prefetch_func (impl=0x7fd4aa0890) at ir3_nir_lower_tex_prefetch.c:218
 #12 in ir3_nir_lower_tex_prefetch (shader=0x7fd4942b10) at ir3_nir_lower_tex_prefetch.c:242

Cc: mesa-stable

Signed-off-by: Danylo Piliaiev <dpiliaiev@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25096>
(cherry picked from commit b16472fc97)
2023-09-12 14:26:47 +01:00
..
.gitlab-ci freedreno+tu: Big GMEM support 2023-03-18 18:21:53 +00:00
afuc freedreno/afuc: Add raw mode for disasm 2023-03-25 16:21:28 +00:00
ci freedreno/a3-5xx: Don't try to emit ISAM for SSBO loads. 2023-08-18 12:08:46 +01:00
common freedreno: Fix or/and'ing two BitmaskEnums 2023-04-01 13:53:31 +00:00
computerator freedreno/computerator: Add support for a7xx 2023-03-30 23:40:48 +00:00
decode freedreno/decode: fix possible overflow 2023-03-23 18:56:34 +00:00
drm freedreno/drm: Don't try to export suballoc bo 2023-06-28 16:08:11 +01:00
drm-shim freedreno/drm-shim: add a660 2022-07-22 02:11:14 +00:00
ds freedreno/pps: Fix a signed/unsigned complaint. 2023-01-18 05:04:46 +00:00
fdl freedreno/a6xx: Fix designator initializer order 2023-03-13 17:31:23 +00:00
ir2
ir3 ir3/lower_tex_prefetch: Fix crash with lowered load_barycentric_at_offset 2023-09-12 14:26:47 +01:00
isa ir3: Add cat7 sleep instruction 2023-02-21 19:59:14 +00:00
perfcntrs freedreno/drm: Return fence from submit flush 2022-12-17 19:14:12 +00:00
registers freedreno/regs: Rename SP_FS_CTRL_REG0.DIFF_FINE into LODPIXMASK 2023-07-21 18:07:53 +01:00
rnn freedreno/rnn: Fix reg names for regs with variants 2023-03-23 17:54:57 +00:00
vulkan vulkan/wsi: add vk_wsi_force_swapchain_to_current_extent driconf 2023-09-06 18:43:04 +01:00
.clang-format
.dir-locals.el
.editorconfig
meson.build ci/freedreno: do not build tools executables without explicitly enabling them 2023-03-23 18:56:34 +00:00