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1259f6d802
A couple patches later in this series use the flag to avoid a few thousand shader-db regresions on all vec4 platforms. I'm not particularly enamored with the name of this flag. However, I suspect the Intel vec4 backend is the only backend that will benefit from it. Specifically, the cases where this helps are all cases where we want to prevent nir_opt_algebraic from rearranging instructions to create 3-source instructions, such as ffma and flrp, with additional immediate value or uniform sources. The earlier commit "intel/vec4: Try to emit a single load for multiple 3-src instruction operands" solves most of the problems caused by additional immediate values, but the restrictions on register strides that cause problems for uniforms and shader inputs persist. Reviewed-by: Matt Turner <mattst88@gmail.com> |
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| dev | ||
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| isl | ||
| perf | ||
| tools | ||
| vulkan | ||
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| Android.mk | ||
| Android.perf.mk | ||
| Android.vulkan.mk | ||
| Makefile.perf.am | ||
| Makefile.sources | ||
| meson.build | ||