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isl: Don't align phys_level0_sa by block dimension
Aligning phys_level0_sa by the compression block dimension prior to
mipmap layout causes the layout of compressed surfaces to differ from
the sampler's expectations in certain cases. The hardware docs agree:
From the BDW PRM, Vol. 5, Compressed Mipmap Layout,
The compressed mipmaps are stored in a similar fashion to
uncompressed mipmaps [...]
The following exceptions apply to the layout of compressed (vs.
uncompressed) mipmaps:
* [...]
* The dimensions of the mip maps are first determined by applying
the sizing algorithm presented in Non-Power-of-Two Mipmaps
above. Then, if necessary, they are padded out to compression
block boundaries.
The last bullet indicates that alignment should not be done for
calculating a miplevel's dimensions, but rather for determining miplevel
placement/padding. Comply with this text by removing the extra
alignment.
Fixes some fbo-generatemipmap-formats piglit failures on all tested
platforms (SNB-KBL).
v2:
- Note fixed platforms.
- Update some consumers via a helper function.
Cc: <mesa-stable@lists.freedesktop.org>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
This commit is contained in:
Nanley Chery
Nanley Chery
parent
fb1350c76f
commit
02f6995d76
2 changed files with 19 additions and 31 deletions
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@ -717,7 +717,7 @@ isl_surf_choose_dim_layout(const struct isl_device *dev,
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/**
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* Calculate the physical extent of the surface's first level, in units of
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* surface samples. The result is aligned to the format's compression block.
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* surface samples.
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*/
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static void
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isl_calc_phys_level0_extent_sa(const struct isl_device *dev,
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@ -746,8 +746,8 @@ isl_calc_phys_level0_extent_sa(const struct isl_device *dev,
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case ISL_DIM_LAYOUT_GEN4_2D:
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case ISL_DIM_LAYOUT_GEN6_STENCIL_HIZ:
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*phys_level0_sa = (struct isl_extent4d) {
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.w = isl_align_npot(info->width, fmtl->bw),
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.h = fmtl->bh,
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.w = info->width,
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.h = 1,
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.d = 1,
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.a = info->array_len,
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};
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@ -771,8 +771,8 @@ isl_calc_phys_level0_extent_sa(const struct isl_device *dev,
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assert(info->samples == 1);
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*phys_level0_sa = (struct isl_extent4d) {
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.w = isl_align_npot(info->width, fmtl->bw),
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.h = isl_align_npot(info->height, fmtl->bh),
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.w = info->width,
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.h = info->height,
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.d = 1,
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.a = info->array_len,
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};
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@ -807,9 +807,6 @@ isl_calc_phys_level0_extent_sa(const struct isl_device *dev,
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isl_msaa_interleaved_scale_px_to_sa(info->samples,
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&phys_level0_sa->w,
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&phys_level0_sa->h);
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phys_level0_sa->w = isl_align(phys_level0_sa->w, fmtl->bw);
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phys_level0_sa->h = isl_align(phys_level0_sa->h, fmtl->bh);
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break;
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}
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break;
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@ -832,8 +829,8 @@ isl_calc_phys_level0_extent_sa(const struct isl_device *dev,
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assert(ISL_DEV_GEN(dev) >= 9);
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*phys_level0_sa = (struct isl_extent4d) {
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.w = isl_align_npot(info->width, fmtl->bw),
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.h = isl_align_npot(info->height, fmtl->bh),
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.w = info->width,
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.h = info->height,
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.d = 1,
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.a = info->depth,
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};
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@ -842,8 +839,8 @@ isl_calc_phys_level0_extent_sa(const struct isl_device *dev,
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case ISL_DIM_LAYOUT_GEN4_3D:
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assert(ISL_DEV_GEN(dev) < 9);
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*phys_level0_sa = (struct isl_extent4d) {
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.w = isl_align(info->width, fmtl->bw),
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.h = isl_align(info->height, fmtl->bh),
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.w = info->width,
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.h = info->height,
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.d = info->depth,
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.a = 1,
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};
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@ -968,13 +965,10 @@ isl_calc_phys_slice0_extent_sa_gen4_2d(
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const struct isl_extent4d *phys_level0_sa,
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struct isl_extent2d *phys_slice0_sa)
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{
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const struct isl_format_layout *fmtl = isl_format_get_layout(info->format);
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assert(phys_level0_sa->depth == 1);
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if (info->levels == 1) {
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/* Do not pad the surface to the image alignment. Instead, pad it only
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* to the pixel format's block alignment.
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/* Do not pad the surface to the image alignment.
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*
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* For tiled surfaces, using a reduced alignment here avoids wasting CPU
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* cycles on the below mipmap layout caluclations. Reducing the
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@ -989,8 +983,8 @@ isl_calc_phys_slice0_extent_sa_gen4_2d(
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* VkBufferImageCopy::bufferRowLength.
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*/
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*phys_slice0_sa = (struct isl_extent2d) {
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.w = isl_align_npot(phys_level0_sa->w, fmtl->bw),
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.h = isl_align_npot(phys_level0_sa->h, fmtl->bh),
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.w = phys_level0_sa->w,
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.h = phys_level0_sa->h,
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};
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return;
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}
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@ -1055,9 +1049,9 @@ isl_calc_phys_total_extent_el_gen4_2d(
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array_pitch_span,
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&phys_slice0_sa);
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*total_extent_el = (struct isl_extent2d) {
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.w = isl_assert_div(phys_slice0_sa.w, fmtl->bw),
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.w = isl_align_div_npot(phys_slice0_sa.w, fmtl->bw),
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.h = *array_pitch_el_rows * (phys_level0_sa->array_len - 1) +
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isl_assert_div(phys_slice0_sa.h, fmtl->bh),
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isl_align_div_npot(phys_slice0_sa.h, fmtl->bh),
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};
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}
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@ -1201,7 +1195,7 @@ isl_calc_phys_total_extent_el_gen9_1d(
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{
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MAYBE_UNUSED const struct isl_format_layout *fmtl = isl_format_get_layout(info->format);
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assert(phys_level0_sa->height / fmtl->bh == 1);
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assert(phys_level0_sa->height == 1);
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assert(phys_level0_sa->depth == 1);
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assert(info->samples == 1);
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assert(image_align_sa->w >= fmtl->bw);
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@ -1480,8 +1474,6 @@ isl_surf_init_s(const struct isl_device *dev,
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struct isl_extent4d phys_level0_sa;
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isl_calc_phys_level0_extent_sa(dev, info, dim_layout, tiling, msaa_layout,
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&phys_level0_sa);
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assert(phys_level0_sa.w % fmtl->bw == 0);
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assert(phys_level0_sa.h % fmtl->bh == 0);
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enum isl_array_pitch_span array_pitch_span =
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isl_choose_array_pitch_span(dev, info, dim_layout, &phys_level0_sa);
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@ -1176,7 +1176,7 @@ struct isl_surf {
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/**
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* Physical extent of the surface's base level, in units of physical
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* surface samples and aligned to the format's compression block.
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* surface samples.
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*
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* Consider isl_dim_layout as an operator that transforms a logical surface
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* layout to a physical surface layout. Then
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@ -1907,13 +1907,9 @@ isl_surf_get_phys_level0_el(const struct isl_surf *surf)
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{
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const struct isl_format_layout *fmtl = isl_format_get_layout(surf->format);
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assert(surf->phys_level0_sa.w % fmtl->bw == 0);
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assert(surf->phys_level0_sa.h % fmtl->bh == 0);
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assert(surf->phys_level0_sa.d % fmtl->bd == 0);
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return isl_extent4d(surf->phys_level0_sa.w / fmtl->bw,
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surf->phys_level0_sa.h / fmtl->bh,
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surf->phys_level0_sa.d / fmtl->bd,
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return isl_extent4d(DIV_ROUND_UP(surf->phys_level0_sa.w, fmtl->bw),
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DIV_ROUND_UP(surf->phys_level0_sa.h, fmtl->bh),
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DIV_ROUND_UP(surf->phys_level0_sa.d, fmtl->bd),
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surf->phys_level0_sa.a);
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}
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