Paulo Zanoni 257e1515e3 brw: null-tile sends don't need to skip L3 on Xe2 and newer ... Despite the information in "Overview of Memory Access" (57046), the L3 seems to be smarter on Xe2+. See 4aa3b2d3ad ("anv: LNL+ doesn't need the special flush for sparse"). The behavior is the same both with vm_bind and TR-TT. v2: Add some comments (Caio). Reviewed-by: Caio Oliveira <caio.oliveira@intel.com> Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36150>		2025-08-01 18:47:37 +00:00
..
blorp	intel: move deref_block_size to intel_urb_config	2025-08-01 11:35:05 +00:00
ci	Uprev Piglit to c3a3e29d59e0972650a6d30d20de930c87739c14	2025-07-31 21:05:20 +00:00
common	intel: reuse intel_urb_config for mesh	2025-08-01 11:35:06 +00:00
compiler	brw: null-tile sends don't need to skip L3 on Xe2 and newer	2025-08-01 18:47:37 +00:00
decoder	intel/genxml: Remove support for start/end atttributes	2025-07-23 16:02:14 +00:00
dev	build: avoid redefining unreachable() which is standard in C23	2025-07-31 17:49:42 +00:00
ds	intel/ds: Fix formatting of stage index.	2025-05-08 01:21:25 +00:00
executor	build: avoid redefining unreachable() which is standard in C23	2025-07-31 17:49:42 +00:00
genxml	build: avoid redefining unreachable() which is standard in C23	2025-07-31 17:49:42 +00:00
isl	build: avoid redefining unreachable() which is standard in C23	2025-07-31 17:49:42 +00:00
nullhw-layer	build: avoid redefining unreachable() which is standard in C23	2025-07-31 17:49:42 +00:00
perf	intel: fork exec_node/list -> brw_exec_node/list as a private Intel utility	2025-07-31 20:23:02 +00:00
shaders	intel: use common CL args	2025-03-06 00:43:59 +00:00
tools	build: avoid redefining unreachable() which is standard in C23	2025-07-31 17:49:42 +00:00
vulkan	treewide: use nir_def_block	2025-08-01 15:34:24 +00:00
vulkan_hasvk	treewide: use nir_def_block	2025-08-01 15:34:24 +00:00
meson.build	intel: Add meson option -Dintel-elk	2025-01-30 00:45:59 +00:00