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brw: null-tile sends don't need to skip L3 on Xe2 and newer

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Despite the information in "Overview of Memory Access" (57046), the L3
seems to be smarter on Xe2+. See 4aa3b2d3ad ("anv: LNL+ doesn't need
the special flush for sparse").

The behavior is the same both with vm_bind and TR-TT.

v2: Add some comments (Caio).

Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36150>
This commit is contained in:
Paulo Zanoni 2025-07-28 22:43:17 -07:00 • committed by Marge Bot
parent 80f01c03ba
commit 257e1515e3
1 changed files with 9 additions and 3 deletions
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12
src/intel/compiler/brw_lower_logical_sends.cpp
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@ -1589,9 +1589,15 @@ lower_lsc_memory_logical_send(const brw_builder &bld, brw_inst *inst)
unsigned cache_mode =
lsc_opcode_is_atomic(op) ? LSC_CACHE(devinfo, STORE, L1UC_L3WB) :
volatile_access ?
(lsc_opcode_is_store(op) ?
LSC_CACHE(devinfo, STORE, L1UC_L3UC) :
LSC_CACHE(devinfo, LOAD, L1UC_L3UC)) :
(devinfo->ver >= 20 ?
/* Xe2 has a better L3 that can deal with null tiles.*/
(lsc_opcode_is_store(op) ?
LSC_CACHE(devinfo, STORE, L1UC_L3WB) :
LSC_CACHE(devinfo, LOAD, L1UC_L3C)) :
/* On older platforms, all caches have to be bypassed. */
(lsc_opcode_is_store(op) ?
LSC_CACHE(devinfo, STORE, L1UC_L3UC) :
LSC_CACHE(devinfo, LOAD, L1UC_L3UC))) :
lsc_opcode_is_store(op) ? LSC_CACHE(devinfo, STORE, L1STATE_L3MOCS) :
LSC_CACHE(devinfo, LOAD, L1STATE_L3MOCS);