Ganesh Belgur Ramachandra a160ffc8d6 amd/common: skip lane size determination for chips without image opcodes (e.g. gfx940) ... This fixes VAAPI decode performance issues. Fixes: 5b3e1a0532 ("radeonsi: change the compute blit to clear/blit multiple pixels per lane") Reviewed-by: Marek Olšák <marek.olsak@amd.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30273> (cherry picked from commit ec4e5ef0f7)		2024-07-23 22:02:53 +02:00
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addrlib	amd: add GFX v11.5.2 support	2024-07-02 12:05:23 +00:00
ci	radeonsi/ci: skip timing out test	2024-07-21 14:41:55 +02:00
common	amd/common: skip lane size determination for chips without image opcodes (e.g. gfx940)	2024-07-23 22:02:53 +02:00
compiler	aco/gfx11.5: workaround export priority issue	2024-07-23 22:02:52 +02:00
drm-shim	build: pass licensing information in SPDX form	2024-06-29 12:42:49 -07:00
llvm	as/llvm: add s_nops before the ordered add loop and s_wait_alu workaround	2024-07-13 01:32:48 +00:00
registers	amd: add gfx12 register definitions	2024-05-11 22:14:05 -04:00
vpelib	amd/vpelib: support VPE IP v6.1.3	2024-07-02 12:05:23 +00:00
vulkan	radv/meta: create the layout for clear depth/stencil on-demand	2024-07-19 14:53:44 +00:00
meson.build	build: pass licensing information in SPDX form	2024-06-29 12:42:49 -07:00