Natalie Vock 1f6ac3fa93 radv/rt,aco: Always dispatch 1D workgroups for RT ... We will swizzle the workgroups ourselves in the next commit. Removes the need for 1D dispatch workarounds. Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/39142>		2026-01-08 19:49:54 +01:00
..
aco_instruction_selection.h	aco/isel: emit register copies for workgroup ids	2025-12-11 08:06:59 +00:00
aco_isel_cfg.cpp	aco: Add preload_preserved pseudo instruction	2025-11-06 12:09:39 +00:00
aco_isel_helpers.cpp	treewide: use BITSET_*_COUNT	2025-12-16 17:42:10 +00:00
aco_isel_setup.cpp	aco: pass aco_compiler_options to init_program()	2025-12-22 07:34:46 +00:00
aco_select_nir.cpp	treewide: add & use parent instr helpers	2025-11-12 21:22:13 +00:00
aco_select_nir_alu.cpp	nir: add nir_alu_instr_is_exact helper	2026-01-07 09:40:57 +00:00
aco_select_nir_intrinsics.cpp	amd: add and use ac_cu_info::has_vtx_format_alpha_adjust_bug	2025-12-22 07:34:48 +00:00
aco_select_ps_epilog.cpp	aco/gfx6: move mrtz writemask workaround to assembler and handle all mrt	2025-12-12 17:00:51 +00:00
aco_select_ps_prolog.cpp	aco: Add preload_preserved pseudo instruction	2025-11-06 12:09:39 +00:00
aco_select_rt_prolog.cpp	radv/rt,aco: Always dispatch 1D workgroups for RT	2026-01-08 19:49:54 +01:00
aco_select_trap_handler.cpp	aco: pass aco_compiler_options to init_program()	2025-12-22 07:34:46 +00:00
aco_select_vs_prolog.cpp	amd: add and use ac_cu_info::has_vtx_format_alpha_adjust_bug	2025-12-22 07:34:48 +00:00