Karol Herbst d6eb93ba7a ac/nir: fix unaligned single component load/stores ... This fixes two problems: 1. we need to lower the bit_size according to the alignment. 2. num_components could end up being 0, so we need to round up instead. Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/13102 Reviewed-by: Rhys Perry <pendingchaos02@gmail.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/34976> (cherry picked from commit 4f5ce2d5aa) Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/35575>		2025-06-18 17:55:47 +02:00
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addrlib	amd/addrlib: remove the DCC page fault workaround	2025-04-01 03:23:22 -04:00
ci	ci/deqp: fix vulkan video build	2025-04-15 17:23:05 +00:00
common	ac/nir: fix unaligned single component load/stores	2025-06-18 17:55:47 +02:00
compiler	aco: do not use v_cvt_pk_u8_f32 for f2u8	2025-06-18 17:55:45 +02:00
drm-shim	amd/drm-shim: add gfx1201	2025-03-10 11:21:36 +00:00
gmlib	amd/gmlib: add gmlib for radeonsi	2025-02-27 03:15:16 +00:00
llvm	ac/llvm: convert to integer after reductions	2025-06-18 17:55:47 +02:00
registers	amd: Rename GFX1103_R1/R2 to PHOENIX/2	2024-11-20 02:14:40 +00:00
vpelib	amd/vpelib: More parameters to the segmentation process and introduce validation hook	2025-03-06 02:11:53 +00:00
vulkan	radv: fix 1x user sample locations on GFX10+	2025-06-18 17:55:47 +02:00
meson.build	amd/gmlib: add gmlib for radeonsi	2025-02-27 03:15:16 +00:00