Samuel Pitoiset 1c286db14e radv: zero-initialize radv_shader_info earlier for graphics pipeline ... This should allow us to remove a big memset when compiling a graphics pipeline. This is mostly for imported NIR stages which don't go through radv_pipeline_stage_init(). Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20947>		2023-03-13 08:11:10 +01:00
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addrlib	amd: split GFX1103 into GFX1103_R1 and GFX1103_R2	2023-02-03 00:18:01 +00:00
ci	ci/amd: move skqp and va jobs on raven from XOrg to the XWayland	2023-03-11 14:48:20 +00:00
common	radv: use 1ull for alignment computations	2023-03-08 23:32:37 +00:00
compiler	aco/spill: allow for disconnected CFG	2023-03-12 18:07:18 +00:00
drm-shim	r300: use drm_shim_override	2022-11-16 14:37:47 +00:00
llvm	amd/llvm,radeonsi/gfx11: switch to using GDS_STRMOUT registers	2023-03-07 22:08:47 +00:00
registers	amd/registers: only define SPI and COMPUTE registers in the 0xB000 range	2023-02-24 21:27:24 +00:00
vulkan	radv: zero-initialize radv_shader_info earlier for graphics pipeline	2023-03-13 08:11:10 +01:00
.clang-format	radv: Add nir_foreach_variable_with_modes to .clang-format	2022-12-09 07:07:10 +00:00
meson.build	meson: build radeon drm-shim also for r300 and r600	2022-11-16 14:37:47 +00:00