Tapani Pälli 0813c1a6fa intel/genxml: set unused 3DSTATE_PS_EXTRA field as mbz ... Wa_14015360517 mentions situations where HW produces invalid occlusion query results when "Pixel Shader Does not write to RT" bit is set. "When Pixel Shader Kills Pixel is set, SW must perform a dummy render target write from the shader and not set this bit, so that Occlusion Query is correct." Another situation is when writing to UAV or to NULL render target. Patch sets field as 'must be zero' to discourage possible use of it. Signed-off-by: Tapani Pälli <tapani.palli@intel.com> Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20849>		2023-01-24 10:28:15 +00:00
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blorp	intel/blorp: Lower base_workgroup_id to zero	2023-01-18 12:21:03 +00:00
ci	ci/piglit: Add some common piglit skips for Mesa CI's testing of glx.	2023-01-24 00:13:02 +00:00
common	intel: use a shared UUID with other drivers	2023-01-17 17:36:07 +02:00
compiler	intel/fs: avoid cmod optimization on instruction with different write_mask	2023-01-24 07:35:42 +00:00
dev	intel/dev: Split hwconfig i915 specific code	2023-01-20 17:26:08 +00:00
ds	intel/utrace: document tracepoints	2023-01-13 01:22:15 +00:00
genxml	intel/genxml: set unused 3DSTATE_PS_EXTRA field as mbz	2023-01-24 10:28:15 +00:00
isl	intel/isl: Disable CCS on MTL until B0 (Wa_14017353530)	2022-12-15 11:43:00 -08:00
nullhw-layer	utils: Merge util/debug.* into util/u_debug.* and remove util/debug.*	2022-11-02 07:25:39 +00:00
perf	intel: add MTL performance metrics	2022-12-09 09:13:02 +00:00
tools	anv,hasvk: migrate align32 to the right functions from util	2023-01-06 17:22:16 +00:00
vulkan	anv: fix preemption enable emission in gpu_memcpy	2023-01-20 22:35:41 +02:00
vulkan_hasvk	hasvk: check the return value of anv_execbuf_add_bo_bitset()	2023-01-23 20:43:36 +00:00
meson.build	intel: Disable SSE2 instruction set if building for non x86 architectures	2022-11-23 16:57:23 +00:00