Rohan Garg 16d061d3ac anv: Enable 16 bit float ops on devices that have a LSC ... Signed-off-by: Rohan Garg <rohan.garg@intel.com> Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17988>		2022-10-17 15:56:29 +02:00
..
blorp	blorp: Fix typo in blorp_xy_block_copy_blt	2022-09-28 08:41:35 +00:00
ci	ci/traces: Blender demo (Cube Diorama) flakes on Intel APL	2022-10-14 18:44:30 +00:00
common	intel: Add and use intel_engines_class_to_string()	2022-10-15 20:04:51 +00:00
compiler	intel/compiler: Support 16 bit float ops	2022-10-17 15:56:28 +02:00
dev	intel: Convert missing i915 engine types to intel	2022-10-15 20:04:51 +00:00
ds	intel: Convert i915 engine type to intel in tools/ common/ and ds/	2022-10-15 20:04:51 +00:00
genxml	intel/genxml: use Path.replace instead of unlink and rename	2022-10-12 10:59:15 -07:00
isl	isl: avoid gfx version switch cases on the hot path	2022-10-14 23:03:16 +00:00
nullhw-layer	util/mesa/wide: Rename _SIMPLE_MTX_INITIALIZER_NP to SIMPLE_MTX_INITIALIZER	2022-10-14 03:27:41 +00:00
perf	intel: fix typos found by codespell	2022-06-27 10:20:55 +00:00
tools	intel: Convert i915 engine type to intel in tools/ common/ and ds/	2022-10-15 20:04:51 +00:00
vulkan	anv: Enable 16 bit float ops on devices that have a LSC	2022-10-17 15:56:29 +02:00
vulkan_hasvk	intel: Add and use intel_engines_class_to_string()	2022-10-15 20:04:51 +00:00
meson.build	intel: add a hasvk vulkan driver	2022-09-02 09:40:45 +00:00