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intel: Convert missing i915 engine types to intel

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This convertions were missed due to bad rebased in my end, sorry.

Fixes: 03b959286e ("intel: Make engine related functions and types not i915 dependent")
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18975>
This commit is contained in:
José Roberto de Souza 2022-10-05 12:46:31 -07:00 • committed by Marge Bot
parent ac2964dfbd
commit 5269d91efc
15 changed files with 25 additions and 27 deletions
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2
src/gallium/drivers/iris/iris_batch.c
View file

@ -239,7 +239,7 @@ iris_init_batch(struct iris_context *ice,
batch->decoder.surface_base = IRIS_MEMZONE_BINDER_START;
batch->decoder.max_vbo_decoded_lines = 32;
if (batch->name == IRIS_BATCH_BLITTER)
batch->decoder.engine = I915_ENGINE_CLASS_COPY;
batch->decoder.engine = INTEL_ENGINE_CLASS_COPY;
}
iris_init_batch_measure(ice, batch);

2
src/intel/common/intel_gem.c
View file

@ -68,7 +68,7 @@ intel_gem_create_context_engines(int fd,
I915_DEFINE_CONTEXT_PARAM_ENGINES(engines_param, 64);
engines_param.extensions = 0;
/* For each type of drm_i915_gem_engine_class of interest, we keep track of
/* For each type of intel_engine_class of interest, we keep track of
* the previous engine instance used.
*/
int last_engine_idx[] = {

8
src/intel/dev/intel_device_info.c
View file

@ -1921,16 +1921,16 @@ init_max_scratch_ids(struct intel_device_info *devinfo)
static unsigned
intel_device_info_calc_engine_prefetch(const struct intel_device_info *devinfo,
enum drm_i915_gem_engine_class engine_class)
enum intel_engine_class engine_class)
{
if (devinfo->verx10 < 125)
return 512;
if (intel_device_info_is_mtl(devinfo)) {
switch (engine_class) {
case I915_ENGINE_CLASS_RENDER:
case INTEL_ENGINE_CLASS_RENDER:
return 2048;
case I915_ENGINE_CLASS_COMPUTE:
case INTEL_ENGINE_CLASS_COMPUTE:
return 1024;
default:
return 512;
@ -2063,7 +2063,7 @@ intel_get_device_info_from_fd(int fd, struct intel_device_info *devinfo)
init_max_scratch_ids(devinfo);
for (enum drm_i915_gem_engine_class engine = I915_ENGINE_CLASS_RENDER;
for (enum intel_engine_class engine = INTEL_ENGINE_CLASS_RENDER;
engine < ARRAY_SIZE(devinfo->engine_class_prefetch); engine++)
devinfo->engine_class_prefetch[engine] =
intel_device_info_calc_engine_prefetch(devinfo, engine);

8
src/intel/dev/intel_device_info.h
View file

@ -28,17 +28,15 @@
#include <stdbool.h>
#include <stdint.h>
#include "drm-uapi/i915_drm.h"
#include "util/macros.h"
#include "compiler/shader_enums.h"
#include "intel/common/intel_engine.h"
#ifdef __cplusplus
extern "C" {
#endif
struct drm_i915_query_topology_info;
#define INTEL_DEVICE_MAX_NAME_SIZE 64
#define INTEL_DEVICE_MAX_SLICES 8
#define INTEL_DEVICE_MAX_SUBSLICES (8) /* Maximum on gfx11 */
@ -351,7 +349,7 @@ struct intel_device_info
* Size of the command streamer prefetch. This is important to know for
* self modifying batches.
*/
unsigned engine_class_prefetch[I915_ENGINE_CLASS_COMPUTE + 1];
unsigned engine_class_prefetch[INTEL_ENGINE_CLASS_COMPUTE + 1];
/**
* For the longest time the timestamp frequency for Gen's timestamp counter

2
src/intel/dev/intel_device_info_override_test.c
View file

@ -71,7 +71,7 @@ main(int argc, char *argv[])
fprintf(stderr, "%u\n", devinfo.verx10);
assert(devinfo.verx10 == verx10);
verify_device_info(&devinfo);
assert(devinfo.engine_class_prefetch[I915_ENGINE_CLASS_RENDER] > 0);
assert(devinfo.engine_class_prefetch[INTEL_ENGINE_CLASS_RENDER] > 0);
}
return 0;

2
src/intel/vulkan/anv_batch_chain.c
View file

@ -936,7 +936,7 @@ anv_cmd_buffer_end_batch_buffer(struct anv_cmd_buffer *cmd_buffer)
*/
if (cmd_buffer->batch_bos.next == cmd_buffer->batch_bos.prev) {
const struct intel_device_info *devinfo = cmd_buffer->device->info;
const enum drm_i915_gem_engine_class engine_class = cmd_buffer->queue_family->engine_class;
const enum intel_engine_class engine_class = cmd_buffer->queue_family->engine_class;
/* Careful to have everything in signed integer. */
int32_t prefetch_len = devinfo->engine_class_prefetch[engine_class];
int32_t batch_len = cmd_buffer->batch.next - cmd_buffer->batch.start;

2
src/intel/vulkan/anv_device.c
View file

@ -687,7 +687,7 @@ anv_physical_device_init_queue_families(struct anv_physical_device *pdevice)
if (env_var_as_boolean("INTEL_COMPUTE_CLASS", false))
c_count = intel_engines_count(pdevice->engine_info,
INTEL_ENGINE_CLASS_COMPUTE);
enum drm_i915_gem_engine_class compute_class =
enum intel_engine_class compute_class =
c_count < 1 ? INTEL_ENGINE_CLASS_RENDER : INTEL_ENGINE_CLASS_COMPUTE;
anv_override_engine_counts(&gc_count, &g_count, &c_count);

2
src/intel/vulkan/genX_query.c
View file

@ -1014,7 +1014,7 @@ void genX(CmdBeginQueryIndexedEXT)(
assert(reloc_idx == pdevice->n_perf_query_commands);
const struct intel_device_info *devinfo = cmd_buffer->device->info;
const enum drm_i915_gem_engine_class engine_class = cmd_buffer->queue_family->engine_class;
const enum intel_engine_class engine_class = cmd_buffer->queue_family->engine_class;
mi_self_mod_barrier(&b, devinfo->engine_class_prefetch[engine_class]);
anv_batch_emit(&cmd_buffer->batch, GENX(PIPE_CONTROL), pc) {

2
src/intel/vulkan_hasvk/anv_batch_chain.c
View file

@ -1019,7 +1019,7 @@ anv_cmd_buffer_end_batch_buffer(struct anv_cmd_buffer *cmd_buffer)
*/
if (cmd_buffer->batch_bos.next == cmd_buffer->batch_bos.prev) {
const struct intel_device_info *devinfo = cmd_buffer->device->info;
const enum drm_i915_gem_engine_class engine_class = cmd_buffer->queue_family->engine_class;
const enum intel_engine_class engine_class = cmd_buffer->queue_family->engine_class;
/* Careful to have everything in signed integer. */
int32_t prefetch_len = devinfo->engine_class_prefetch[engine_class];
int batch_len = cmd_buffer->batch.next - cmd_buffer->batch.start;

6
src/intel/vulkan_hasvk/anv_device.c
View file

@ -696,7 +696,7 @@ anv_physical_device_init_queue_families(struct anv_physical_device *pdevice)
.queueFlags = VK_QUEUE_GRAPHICS_BIT |
VK_QUEUE_TRANSFER_BIT,
.queueCount = g_count,
.engine_class = I915_ENGINE_CLASS_RENDER,
.engine_class = INTEL_ENGINE_CLASS_RENDER,
};
}
if (c_count > 0) {
@ -704,7 +704,7 @@ anv_physical_device_init_queue_families(struct anv_physical_device *pdevice)
.queueFlags = VK_QUEUE_COMPUTE_BIT |
VK_QUEUE_TRANSFER_BIT,
.queueCount = c_count,
.engine_class = I915_ENGINE_CLASS_RENDER,
.engine_class = INTEL_ENGINE_CLASS_RENDER,
};
}
/* Increase count below when other families are added as a reminder to
@ -718,7 +718,7 @@ anv_physical_device_init_queue_families(struct anv_physical_device *pdevice)
VK_QUEUE_COMPUTE_BIT |
VK_QUEUE_TRANSFER_BIT,
.queueCount = 1,
.engine_class = I915_ENGINE_CLASS_RENDER,
.engine_class = INTEL_ENGINE_CLASS_RENDER,
};
family_count = 1;
}

2
src/intel/vulkan_hasvk/anv_perf.c
View file

@ -353,7 +353,7 @@ VkResult anv_EnumeratePhysicalDeviceQueueFamilyPerformanceQueryCountersKHR(
*/
struct anv_queue_family *queue_family =
&pdevice->queue.families[queueFamilyIndex];
if (queue_family->engine_class != I915_ENGINE_CLASS_RENDER)
if (queue_family->engine_class != INTEL_ENGINE_CLASS_RENDER)
return vk_outarray_status(&out);
for (int c = 0; c < (perf ? perf->n_counters : 0); c++) {

2
src/intel/vulkan_hasvk/anv_private.h
View file

@ -927,7 +927,7 @@ struct anv_queue_family {
uint32_t queueCount;
/* Driver internal information */
enum drm_i915_gem_engine_class engine_class;
enum intel_engine_class engine_class;
};
#define ANV_MAX_QUEUE_FAMILIES 3

8
src/intel/vulkan_hasvk/anv_utrace.c
View file

@ -267,13 +267,13 @@ static const char *
queue_family_to_name(const struct anv_queue_family *family)
{
switch (family->engine_class) {
case I915_ENGINE_CLASS_RENDER:
case INTEL_ENGINE_CLASS_RENDER:
return "render";
case I915_ENGINE_CLASS_COPY:
case INTEL_ENGINE_CLASS_COPY:
return "copy";
case I915_ENGINE_CLASS_VIDEO:
case INTEL_ENGINE_CLASS_VIDEO:
return "video";
case I915_ENGINE_CLASS_VIDEO_ENHANCE:
case INTEL_ENGINE_CLASS_VIDEO_ENHANCE:
return "video-enh";
default:
return "unknown";

2
src/intel/vulkan_hasvk/genX_query.c
View file

@ -1016,7 +1016,7 @@ void genX(CmdBeginQueryIndexedEXT)(
assert(reloc_idx == pdevice->n_perf_query_commands);
const struct intel_device_info *devinfo = cmd_buffer->device->info;
const enum drm_i915_gem_engine_class engine_class = cmd_buffer->queue_family->engine_class;
const enum intel_engine_class engine_class = cmd_buffer->queue_family->engine_class;
mi_self_mod_barrier(&b, devinfo->engine_class_prefetch[engine_class]);
anv_batch_emit(&cmd_buffer->batch, GENX(PIPE_CONTROL), pc) {

2
src/intel/vulkan_hasvk/genX_state.c
View file

@ -425,7 +425,7 @@ genX(init_device_state)(struct anv_device *device)
for (uint32_t i = 0; i < device->queue_count; i++) {
struct anv_queue *queue = &device->queues[i];
switch (queue->family->engine_class) {
case I915_ENGINE_CLASS_RENDER:
case INTEL_ENGINE_CLASS_RENDER:
res = init_render_queue_state(queue);
break;
default: