mesa/src/imagination/rogue
Simon Perretta 81af999a75 pvr: Clarify unreachable text
Signed-off-by: Simon Perretta <simon.perretta@imgtec.com>
Acked-by: Frank Binns <frank.binns@imgtec.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20430>
2023-02-08 15:15:17 +00:00
..
nir pvr: Add new Rogue compiler framework 2023-02-08 15:15:17 +00:00
passes pvr: Clarify unreachable text 2023-02-08 15:15:17 +00:00
tools pvr: Clarify unreachable text 2023-02-08 15:15:17 +00:00
meson.build pvr: Add new Rogue compiler framework 2023-02-08 15:15:17 +00:00
rogue.c pvr: Clarify unreachable text 2023-02-08 15:15:17 +00:00
rogue.h pvr: Clarify unreachable text 2023-02-08 15:15:17 +00:00
rogue_alu_instrs.def pvr: Support dual-destination ALU instructions 2023-02-08 15:15:17 +00:00
rogue_backend_instrs.def pvr: Add new Rogue compiler framework 2023-02-08 15:15:17 +00:00
rogue_bitwise_instrs.def pvr: Add new Rogue compiler framework 2023-02-08 15:15:17 +00:00
rogue_build_data.c pvr: Clarify unreachable text 2023-02-08 15:15:17 +00:00
rogue_builder.c pvr: Support dual-destination ALU instructions 2023-02-08 15:15:17 +00:00
rogue_builder.h pvr: Support dual-destination ALU instructions 2023-02-08 15:15:17 +00:00
rogue_compile.c pvr: Keep NIR SSA defs instead of registers 2023-02-08 15:15:17 +00:00
rogue_constreg.c pvr: Add new Rogue compiler framework 2023-02-08 15:15:17 +00:00
rogue_ctrl_instrs.def pvr: Add new Rogue compiler framework 2023-02-08 15:15:17 +00:00
rogue_debug.c pvr: Add new Rogue compiler framework 2023-02-08 15:15:17 +00:00
rogue_encode.c pvr: Clarify unreachable text 2023-02-08 15:15:17 +00:00
rogue_info.c pvr: Validate instruction repeat and src/dst sizes 2023-02-08 15:15:17 +00:00
rogue_isa.h pvr: Add new Rogue compiler framework 2023-02-08 15:15:17 +00:00
rogue_nir.c pvr: Keep NIR SSA defs instead of registers 2023-02-08 15:15:17 +00:00
rogue_print.c pvr: Clarify unreachable text 2023-02-08 15:15:17 +00:00
rogue_validate.c pvr: Add block printing support during validation 2023-02-08 15:15:17 +00:00