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pvr: Keep NIR SSA defs instead of registers
Signed-off-by: Simon Perretta <simon.perretta@imgtec.com> Acked-by: Frank Binns <frank.binns@imgtec.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20430>
This commit is contained in:
Simon Perretta
Marge Bot
parent
d47d0ea101
commit
d431adaecd
2 changed files with 48 additions and 49 deletions
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@ -51,6 +51,18 @@ static void trans_nir_jump(rogue_builder *b, nir_jump_instr *jump)
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unreachable("Unimplemented NIR jump instruction type.");
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}
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static void trans_nir_load_const(rogue_builder *b,
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nir_load_const_instr *load_const)
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{
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rogue_reg *dst = rogue_ssa_reg(b->shader, load_const->def.index);
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if (load_const->def.bit_size == 32) {
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uint32_t imm = nir_const_value_as_uint(load_const->value[0], 32);
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rogue_MOV(b, rogue_ref_reg(dst), rogue_ref_imm(imm));
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} else {
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unreachable("Unimplemented NIR load_const bit size.");
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}
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}
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static void trans_nir_intrinsic_load_input_fs(rogue_builder *b,
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nir_intrinsic_instr *intr)
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{
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@ -59,7 +71,7 @@ static void trans_nir_intrinsic_load_input_fs(rogue_builder *b,
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unsigned load_size = nir_dest_num_components(intr->dest);
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assert(load_size == 1); /* TODO: We can support larger load sizes. */
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rogue_reg *dst = rogue_ssa_reg(b->shader, intr->dest.reg.reg->index);
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rogue_reg *dst = rogue_ssa_reg(b->shader, intr->dest.ssa.index);
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struct nir_io_semantics io_semantics = nir_intrinsic_io_semantics(intr);
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unsigned component = nir_intrinsic_component(intr);
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@ -90,7 +102,7 @@ static void trans_nir_intrinsic_load_input_vs(rogue_builder *b,
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ASSERTED unsigned load_size = nir_dest_num_components(intr->dest);
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assert(load_size == 1); /* TODO: We can support larger load sizes. */
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rogue_reg *dst = rogue_ssa_reg(b->shader, intr->dest.reg.reg->index);
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rogue_reg *dst = rogue_ssa_reg(b->shader, intr->dest.ssa.index);
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struct nir_io_semantics io_semantics = nir_intrinsic_io_semantics(intr);
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unsigned component = nir_intrinsic_component(intr);
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@ -127,14 +139,13 @@ static void trans_nir_intrinsic_store_output_fs(rogue_builder *b,
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ASSERTED unsigned store_size = nir_src_num_components(intr->src[0]);
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assert(store_size == 1);
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nir_const_value *const_value = nir_src_as_const_value(intr->src[1]);
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/* TODO: When hoisting I/O allocation to the driver, check if this is
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* correct.
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*/
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unsigned pixout_index = nir_const_value_as_uint(*const_value, 32);
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unsigned pixout_index = nir_src_as_uint(intr->src[1]);
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rogue_reg *dst = rogue_pixout_reg(b->shader, pixout_index);
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rogue_reg *src = rogue_ssa_reg(b->shader, intr->src[0].reg.reg->index);
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rogue_reg *src = rogue_ssa_reg(b->shader, intr->src[0].ssa->index);
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rogue_instr *instr =
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&rogue_MOV(b, rogue_ref_reg(dst), rogue_ref_reg(src))->instr;
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@ -156,7 +167,7 @@ static void trans_nir_intrinsic_store_output_vs(rogue_builder *b,
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component);
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rogue_reg *dst = rogue_vtxout_reg(b->shader, vtxout_index);
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rogue_reg *src = rogue_ssa_reg(b->shader, intr->src[0].reg.reg->index);
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rogue_reg *src = rogue_ssa_reg(b->shader, intr->src[0].ssa->index);
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rogue_instr *instr =
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&rogue_MOV(b, rogue_ref_reg(dst), rogue_ref_reg(src))->instr;
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@ -192,7 +203,7 @@ static void trans_nir_intrinsic_load_ubo(rogue_builder *b,
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unsigned sh_index = rogue_ubo_reg(ubo_data, desc_set, binding, offset);
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rogue_reg *dst = rogue_ssa_reg(b->shader, intr->dest.reg.reg->index);
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rogue_reg *dst = rogue_ssa_reg(b->shader, intr->dest.ssa.index);
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rogue_reg *src = rogue_shared_reg(b->shader, sh_index);
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rogue_instr *instr =
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&rogue_MOV(b, rogue_ref_reg(dst), rogue_ref_reg(src))->instr;
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@ -220,9 +231,9 @@ static void trans_nir_intrinsic(rogue_builder *b, nir_intrinsic_instr *intr)
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static void trans_nir_alu_pack_unorm_4x8(rogue_builder *b, nir_alu_instr *alu)
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{
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rogue_reg *dst = rogue_ssa_reg(b->shader, alu->dest.dest.reg.reg->index);
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rogue_reg *dst = rogue_ssa_reg(b->shader, alu->dest.dest.ssa.index);
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rogue_regarray *src_array =
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rogue_ssa_vec_regarray(b->shader, 4, alu->src[0].src.reg.reg->index, 0);
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rogue_ssa_vec_regarray(b->shader, 4, alu->src[0].src.ssa->index, 0);
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rogue_alu_instr *pck_u8888 =
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rogue_PCK_U8888(b, rogue_ref_reg(dst), rogue_ref_regarray(src_array));
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@ -230,46 +241,21 @@ static void trans_nir_alu_pack_unorm_4x8(rogue_builder *b, nir_alu_instr *alu)
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rogue_set_alu_op_mod(pck_u8888, ROGUE_ALU_OP_MOD_SCALE);
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}
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static void trans_nir_alu_mov(rogue_builder *b, nir_alu_instr *alu)
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{
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rogue_reg *dst;
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unsigned dst_index = alu->dest.dest.reg.reg->index;
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if (alu->dest.dest.reg.reg->num_components > 1) {
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assert(util_is_power_of_two_nonzero(alu->dest.write_mask));
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dst =
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rogue_ssa_vec_reg(b->shader, dst_index, ffs(alu->dest.write_mask) - 1);
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} else {
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dst = rogue_ssa_reg(b->shader, dst_index);
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}
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if (alu->src[0].src.is_ssa) {
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/* Immediate/constant source. */
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nir_const_value *const_value = nir_src_as_const_value(alu->src[0].src);
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unsigned imm = nir_const_value_as_uint(*const_value, 32);
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rogue_MOV(b, rogue_ref_reg(dst), rogue_ref_imm(imm));
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} else {
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/* Register source. */
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rogue_reg *src = rogue_ssa_reg(b->shader, alu->src[0].src.reg.reg->index);
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rogue_MOV(b, rogue_ref_reg(dst), rogue_ref_reg(src));
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}
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}
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static void trans_nir_alu_fmul(rogue_builder *b, nir_alu_instr *alu)
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{
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rogue_reg *dst = rogue_ssa_reg(b->shader, alu->dest.dest.reg.reg->index);
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rogue_reg *src0 = rogue_ssa_reg(b->shader, alu->src[0].src.reg.reg->index);
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rogue_reg *src1 = rogue_ssa_reg(b->shader, alu->src[1].src.reg.reg->index);
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rogue_reg *dst = rogue_ssa_reg(b->shader, alu->dest.dest.ssa.index);
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rogue_reg *src0 = rogue_ssa_reg(b->shader, alu->src[0].src.ssa->index);
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rogue_reg *src1 = rogue_ssa_reg(b->shader, alu->src[1].src.ssa->index);
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rogue_FMUL(b, rogue_ref_reg(dst), rogue_ref_reg(src0), rogue_ref_reg(src1));
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}
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static void trans_nir_alu_ffma(rogue_builder *b, nir_alu_instr *alu)
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{
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rogue_reg *dst = rogue_ssa_reg(b->shader, alu->dest.dest.reg.reg->index);
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rogue_reg *src0 = rogue_ssa_reg(b->shader, alu->src[0].src.reg.reg->index);
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rogue_reg *src1 = rogue_ssa_reg(b->shader, alu->src[1].src.reg.reg->index);
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rogue_reg *src2 = rogue_ssa_reg(b->shader, alu->src[2].src.reg.reg->index);
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rogue_reg *dst = rogue_ssa_reg(b->shader, alu->dest.dest.ssa.index);
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rogue_reg *src0 = rogue_ssa_reg(b->shader, alu->src[0].src.ssa->index);
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rogue_reg *src1 = rogue_ssa_reg(b->shader, alu->src[1].src.ssa->index);
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rogue_reg *src2 = rogue_ssa_reg(b->shader, alu->src[2].src.ssa->index);
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rogue_FMAD(b,
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rogue_ref_reg(dst),
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@ -278,6 +264,19 @@ static void trans_nir_alu_ffma(rogue_builder *b, nir_alu_instr *alu)
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rogue_ref_reg(src2));
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}
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static void trans_nir_alu_vecN(rogue_builder *b, nir_alu_instr *alu, unsigned n)
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{
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unsigned dst_index = alu->dest.dest.ssa.index;
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rogue_reg *dst;
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rogue_reg *src;
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for (unsigned u = 0; u < n; ++u) {
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dst = rogue_ssa_vec_reg(b->shader, dst_index, u);
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src = rogue_ssa_reg(b->shader, alu->src[u].src.ssa->index);
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rogue_MOV(b, rogue_ref_reg(dst), rogue_ref_reg(src));
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}
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}
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static void trans_nir_alu(rogue_builder *b, nir_alu_instr *alu)
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{
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switch (alu->op) {
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@ -285,15 +284,15 @@ static void trans_nir_alu(rogue_builder *b, nir_alu_instr *alu)
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return trans_nir_alu_pack_unorm_4x8(b, alu);
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return;
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case nir_op_mov:
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return trans_nir_alu_mov(b, alu);
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case nir_op_fmul:
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return trans_nir_alu_fmul(b, alu);
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case nir_op_ffma:
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return trans_nir_alu_ffma(b, alu);
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case nir_op_vec4:
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return trans_nir_alu_vecN(b, alu, 4);
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default:
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break;
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}
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@ -352,7 +351,7 @@ rogue_shader *rogue_nir_to_rogue(rogue_build_ctx *ctx, const nir_shader *nir)
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break;
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case nir_instr_type_load_const:
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/* trans_nir_load_const(&b, nir_instr_as_load_const(instr)); */
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trans_nir_load_const(&b, nir_instr_as_load_const(instr));
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break;
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case nir_instr_type_jump:
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@ -105,6 +105,9 @@ static void rogue_nir_passes(struct rogue_build_ctx *ctx,
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/* Lower ALU operations to scalars. */
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NIR_PASS_V(nir, nir_lower_alu_to_scalar, NULL, NULL);
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/* Lower load_consts to scalars. */
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NIR_PASS_V(nir, nir_lower_load_const_to_scalar);
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/* Algebraic opts. */
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do {
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progress = false;
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@ -144,11 +147,8 @@ static void rogue_nir_passes(struct rogue_build_ctx *ctx,
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/* TODO: Investigate this further. */
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/* NIR_PASS_V(nir, nir_opt_move, nir_move_load_ubo | nir_move_load_input); */
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/* Convert vecNs to movs so we can sequentially allocate them later. */
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NIR_PASS_V(nir, nir_lower_vec_to_movs, NULL, NULL);
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/* Out of SSA pass. */
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NIR_PASS_V(nir, nir_convert_from_ssa, false);
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/* NIR_PASS_V(nir, nir_convert_from_ssa, true); */
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/* TODO: Re-enable scheduling after register pressure tweaks. */
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#if 0
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