Samuel Pitoiset 10ef9c6a80 radv: disable RB+ with E5B9G9R9 to workaround failures on GFX10.3-GFX11.5 ... This looks like a hw bug on GFX10.3-GFX11.5 because RB+ seems to only work as expected when all channels (RGBA) are written. With that format, RGB channels must be all set or unset but setting the A channel is legal so far. This will reduce rendering performance with that format but it's the less intrusive solution for now. This might be revisited in the near future, also with more VKCTS coverage. This has been tested and verified on GFX10.3 (NAVI21) and GFX11 (NAVI31) and GFX12 (NAVI48), unfortunately I don't have GFX11.5 but let's assume it's broken there too. Cc: mesa-stable Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/13371 Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/35631>		2025-07-02 17:21:58 +00:00
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addrlib	amd/addrlib: remove the DCC page fault workaround	2025-04-01 03:23:22 -04:00
ci	rusticl: Fix work group size validation	2025-07-01 18:55:01 +00:00
common	treewide: use nir_break_if with named if	2025-06-30 14:51:54 -04:00
compiler	aco/ra: fix repeated compact_linear_vgprs() in get_reg()	2025-07-02 09:26:04 +00:00
drm-shim	amd/drm-shim: add gfx1201	2025-03-10 11:21:36 +00:00
gmlib	amd/gmlib: remove the executable bit	2025-06-12 07:44:27 +00:00
lanczoslib	radeonsi/vpe: enhance scaling quality	2025-06-12 07:44:26 +00:00
llvm	ac/llvm: use ds_bpermute_b32 for GFX12 wave64	2025-06-14 13:59:11 +00:00
registers	amd: Rename GFX1103_R1/R2 to PHOENIX/2	2024-11-20 02:14:40 +00:00
vpelib	amd/vpelib: Fix CodeQL issues Pt1	2025-05-16 11:33:08 +08:00
vulkan	radv: disable RB+ with E5B9G9R9 to workaround failures on GFX10.3-GFX11.5	2025-07-02 17:21:58 +00:00
meson.build	radeonsi/vpe: enhance scaling quality	2025-06-12 07:44:26 +00:00